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US 7,073,026 B2Granted
Microprocessor including cache memory supporting multiple accesses per cycle
AssigneeAdvanced Micro Devices, Inc.
InventorMitchell Alsup
Life of this patent
Estimating the term…
Abstract
A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes a plurality of independently accessible storage blocks. The buses may be coupled to convey a plurality of cache access requests to each of the storage blocks. In response to the plurality of cache access requests being conveyed on the plurality of cache buses, different ones of the storage blocks are concurrently accessible.
Claims51
A microprocessor, comprising:
- an execution unit configured to operate on instructions and data;
- a cache memory subsystem coupled to said execution unit;
- wherein said cache memory subsystem includes:
- a cache memory including a plurality of independently accessible storage blocks;
- a plurality of independently accessible tag units coupled to said plurality of storage blocks and configured to store a plurality of tags each including an address tag value;
- a plurality of cache buses coupled to convey a plurality of cache access requests to each of said plurality of storage blocks;
- and
- a cache controller configured to select said plurality of cache access requests for conveying via said plurality of cache buses;
- wherein said cache controller is further configured to select said plurality of cache access requests such that no cache access conflict exists at any of said plurality of independently accessible tag units;
- and
- wherein in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible.
8 more elements
A cache memory subsystem, comprising:
- a cache memory including a plurality of independently accessible storage blocks;
- a plurality of independently accessible tag units coupled to said plurality of storage blocks and configured to store a plurality of tags each including an address tag value;
- a plurality of cache buses coupled to convey a plurality of cache access requests to each of said plurality of storage blocks;
- a cache controller configured to select said plurality of cache access requests for conveying via said plurality of cache buses;
- wherein said cache controller is further configured to select said plurality of cache access requests such that no cache access conflict exists at any of said plurality of independently accessible tag units;
- and
- wherein in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible.
4 more elements
A computer system, comprising:
- a system memory configured to store instructions and data;
- a microprocessor coupled to said system memory via a memory bus;
- wherein said microprocessor includes:
- an execution unit configured to operate on said instructions and data;
- a cache memory subsystem coupled to said execution unit and configured to store said instructions and data for execution by said execution unit;
- wherein said cache memory subsystem includes:
- a cache memory including a plurality of independently accessible storage blocks;
- a plurality of independently accessible tag units coupled to said plurality of storage blocks and configured to store a plurality of tags each including an address tag value;
- a plurality of cache buses coupled to convey a plurality of cache access requests to each of said plurality of storage blocks;
- and
- a cache controller configured to select said plurality of cache access requests for conveying via said plurality of cache buses;
- wherein said cache controller is further configured to select said plurality of cache access requests such that no cache access conflict exists at any of said plurality of independently accessible tag units;
- and
- wherein in response to said plurality of cache access requests being conveyed on said plurality of cache buses, different ones of said plurality of storage blocks are concurrently accessible.
11 more elements
Dependencies are inferred from the claim text.