Method and apparatus for assembling non-aligned packet fragments over multiple cycles
AssigneeCypress Semiconductor Corporation
InventorsAmitabha Banerjee, Somnath Paul
Life of this patent
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Abstract
A method and apparatus for assembling non-aligned packet fragments over multiple cycles is described. In one embodiment, the invention is a method. The method includes rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment. The method also includes outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment. The method further includes selectively copying the double width image of the rotated data fragment from the bus to a location logically following the prior data fragment in a destination register.
Claims9
An apparatus, comprising:
- a rotate register to receive a data fragment and logically rotate bits of the data fragment;
- a double width bus coupled to the rotate register to receive a double width image of the contents of the rotate register;
- a destination register coupled to the double width bus to receive data of the double width image from the double width bus;
- a write enable mask coupled to the destination register to selectively enable writing to the destination register, and
- a concatenator coupled to the bus to receive the double width image and coupled to the destination register to provide contents of the concatenator to the destination register, wherein
- the destination register is further coupled to the concatenator to selectively provide prior data to the concatenator.
An apparatus, comprising:
- a rotate register to receive a data fragment and logically rotate bits of the data fragment;
- a double width bus coupled to the rotate register to receive a double width image of the contents of the rotate register;
- a destination register coupled to the double width bus to receive data of the double width image from the double width bus, wherein each of the rotate register, the double width bus, and the destination register are included in a fragment assembly module, the fragment assembly module included in a framer, the framer suitable for coupling to a physical link layer and to a network processor.
A method, comprising:
- rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment;
- outputting the rotated data fragment to a double width bus as a double width image of the rotated data fragment;
- selectively copying the double width image of the rotated data fragment from the double width bus to a location logically following the prior data fragment in a destination register, wherein the tail pointer is a pointer to the first bit of the destination register logically following the bits occupied by the prior data fragment;
- copying the prior data fragment into the rotate register;
- and
- unpacking a received data fragment into the non-aligned data fragment.
A method, comprising:
- rotating a non-aligned data fragment within a rotate register based on a tail pointer of a prior data fragment to form a rotated data fragment;
- outpuffing the rotated data fragment to a double width bus as a double width image of the rotated data fragment;
- selectively copying the double width image of the rotated data fragment from the double width bus to a location logically following the prior data fragment in a destination register, wherein the tail pointer is a pointer to the first byte of the destination register logically following the bytes occupied by the prior data fragment;
- copying the prior data fragment into the rotate register;
- and
- unpacking a received data fragment into the non-aligned data fragment.
Dependencies are inferred from the claim text.