# US 7,073,013 B2 · Mass storage device with boot code > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,073,013 B2 - Document ID: US7073013B2 - Status: Granted - Kind: B2 - Application number: 10/611,940 - Filed: 2003-07-03 - Published: 2005-01-06 - Granted: 2006-07-04 - Earliest claimed: 2003-07-03 - Assignees: H-Systems Flash Disk Pioneers Ltd. - Inventors: Menahem Lasser - Web page: https://patentgrep.com/patent/US7073013B2 ## CPC - G06F 9/4406: {Loading of operating system} - G06F 8/60: Software deployment - G06F 9/44573: {Execute-in-place [XIP]} - G06F 21/575: {Secure boot} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory device includes a first, directly executable memory with boot code, a second memory with operating system code, and a common connector. When the device is connected to a computer that lacks a BIOS of its own, the computer boots from the first memory and downloads the operating system from the second memory. A user of a system that includes a plurality of the memory devices and a computer that lacks a BIOS selects an operating system by reversibly connecting the appropriate memory device to the computer. The memory device also serves as a security key for a computer that lacks a BIOS. ## Claims ### Claim 1 A memory device comprising: (a) a first, directly executable memory for storing boot code of a computer, said boot code including code that is executed first by said computer when said computer is powered up; (b) a second memory; and (c) a single connector, for operationally connecting said two memories to said computer, that includes: (i) a first plurality of pins for supporting communication between said first memory and said computer, and (ii) a second plurality of pins for supporting communication between said second memory and said computer, said first and second pluralities of pins sharing at least one said pin; and (d) a switch for alternately connecting said first memory and said second memory to said computer via said at least one shared pin. ### Claim 2 (depends on 1) The device of claim 1, wherein said operational connection is reversible. ### Claim 3 (depends on 1) The device of claim 1, wherein said operational connection is permanent. ### Claim 4 (depends on 1) The device of claim 1, wherein said first memory is a read-only memory. ### Claim 5 (depends on 1) The device of claim 1, wherein said second memory is for storing an operating system of said computer. ### Claim 6 (depends on 1) The device of claim 1, wherein said second memory is a magnetic disk memory. ### Claim 7 (depends on 1) The device of claim 1, wherein said second memory is a flash memory. ### Claim 8 (depends on 1) The device of claim 1, further comprising: (d) a Universal Serial Bus (USB) controller for supporting communication between said second memory and said computer. ### Claim 9 (depends on 8) The device of claim 8, wherein at least one of said memories stores a read-only USB driver. ### Claim 10 (depends on 9) The device of claim 9, wherein said read-only USB driver is stored in said first memory. ### Claim 11 A computer peripheral device comprising: (a) a first component; (b) a second component separate from said first component; (c) a connector, for operationally connecting said first and second components to a computer, that includes: (i) a first plurality of pins for supporting communication between said first component and said computer, and (ii) a second plurality of pins for supporting communication between said second component and said computer, said first and second pluralities of pins sharing at least one said pin; (d) a single Universal Serial Bus (USB) controller for supporting communication only between said first component and said computer; and (e) a switch for alternately connecting said first component and said second component to said computer via said at least one shared pin. ### Claim 12 (depends on 11) The device of claim 11, wherein said first component is a memory. ### Claim 13 (depends on 12) The device of claim 12, wherein said memory is a magnetic disk memory. ### Claim 14 (depends on 12) The device of claim 12, wherein said memory is a flash memory. ### Claim 15 (depends on 11) The device of claim 11, wherein said second component is a directly executable memory for storing boot code. ### Claim 16 (depends on 15) The device of claim 15, wherein said connector supports a Low Pin Count (LPC) protocol for said second component. ### Claim 17 (depends on 15) The device of claim 15, wherein said directly executable memory is a read-only memory. ### Claim 18 (depends on 11) The device of claim 11, wherein said operational connection is reversible. ### Claim 19 (depends on 11) The device of claim 11, wherein said second plurality of pins includes separate respective pins for address signals and data signals. ### Claim 20 A method of operating a computer, comprising the steps of: (a) providing at least one memory device including: (i) a respective first, directly executable memory, and (ii) a respective second memory; (b) for each said at least one memory device, storing boot code of the computer in said respective first memory, said boot code including code that is executed first by the computer when the computer is powered up; (c) operationally connecting one of said at least one memory device to the computer; (d) executing said boot code that is stored in said respective first memory of said one memory device, by the computer and (e) for each said at least one memory device, storing an operating system of the computer in said respective second memory; wherein said executing of said boot code includes copying said operating system from said respective second memory of said one memory device to the computer; wherein, for each said at least one memory device, said boot code includes driver code for said respective second memory; and wherein said copying of said operating system from said respective second memory of said one memory device to the computer is effected by executing at least a portion of said driver code. ### Claim 21 (depends on 20) The method of claim 20, wherein said operational connection is reversible. ### Claim 22 (depends on 20) The method of claim 20, wherein said driver code is read-only driver code. ### Claim 23 (depends on 20) The method of claim 20, wherein a plurality of said memory devices are provided, each said memory device having a respective operating system of the computer stored in said second memory thereof; and wherein all said respective operating systems are different. ### Claim 24 (depends on 20) The method of claim 20, wherein all of said boot code is executed directly from said first memory. ### Claim 25 A memory device comprising: (a) a first, directly executable memory for storing boot code of a computer, said boot code including code that is executed first by said computer when said computer is powered up; (b) a second memory; and (c) a single connector, for operationally connecting said two memories to said computer, that includes: (i) a first plurality of pins for supporting communication between said first memory and said computer, said first plurality of pins being for a first access protocol that supports direct execution of said boot code and (ii) a second plurality of pins for supporting communication between said second memory and said computer, said second plurality of pins being for a second, serial access protocol. ### Claim 26 (depends on 25) The device of claim 25, wherein said first and second pluralities of pins are separate. ### Claim 27 (depends on 25) The device of claim 25, wherein said first protocol is a Low Pin Count (LPC) protocol. ### Claim 28 (depends on 25) The device of claim 25, wherein said second protocol is a Universal Serial Bus (USB) protocol. ### Claim 29 A computer peripheral device comprising: (a) a first component; (b) a second component separate from said first component; (c) a connector, for operationally connecting said first and second components to a computer, that includes: (i) a first plurality of pins for supporting communication between said first component and said computer, and (ii) a second plurality of pins for supporting communication between said second component and said computer, said communication between said second component and said computer multiplexing said second plurality of pins; and (d) a single Universal Serial Bus (USB) controller for supporting communication only between said first component and said computer. ### Claim 30 (depends on 29) The device of claim 29, wherein said first and second pluralities of pins are separate. ### Claim 31 A method of operating a computer, comprising the steps of: (a) providing at least one memory device including: (i) a respective first, directly executable memory, and (ii) a respective second memory; (b) for each said at least one memory device, storing boot code of the computer in said respective first memory, said boot code including code that is executed first by the computer when the computer is powered up; (c) operationally connecting one of said at least one memory device to the computer; and (d) executing said boot code that is stored in said respective first memory of said one memory device, by the computer, by steps including: (i) executing only a portion of said boot code directly from said first memory; (ii) copying a remainder of said boot code to a random access memory; and (iii) executing said reminder of said boot code from said random access memory.