Hierarchical, network-based emulation system

An apparatus for emulating behavior of an electronic device under test (DUT) having a plurality of components, the apparatus comprising:

• a packet routing network for conveying data packets via electronic signals;
• a plurality of first emulation resources, each first emulation resource having a plurality of terminals, and each for emulating a separate component of the electronic equipment by generating output signals at its terminals in response to input signals applied to its terminals, each first emulation resource having a unique network address;
• and
• a first transaction device connected to the packet routing network for transmitting and receiving packets via the packet routing network, and connected to a first portion of the input terminals of each first emulation resource for transmitting input signals to that first emulation resource, for responding to at least one packet transmitted via the bus system identifying one first emulation resource by its network address by communicating with at least one of the identified resource's terminals via signals.

An apparatus for emulating an electronic circuit device under test (DUT), the apparatus comprising:

• a packet routing network for conveying packets;
• and
• at least one resource board comprising
• a printed circuit board (203);
• a plurality of field programmable gate arrays (FPGAs) mounted on the PCB, each for emulating a separate portion of the DUT by receiving input signals and generating output signals, the PCB providing signal paths between the FPGAs;
• and
• a transaction device mounted on the PCB for transmitting outgoing packets via the packet routing network indicating states of output signals of the FPGAs and for receiving incoming packets arriving via the packet routing network, and for driving input signals of the FPGAs to states indicated by data included the incoming packets wherein each FPGA is identified by a unique network address and wherein packets conveyed via the packet routing network include network addresses identifying individual FPGAs.

An apparatus for emulating a test bench, the apparatus comprising:

• a packet routing network for conveying packets;
• a plurality of emulation resources, each having inputs and outputs and each emulating a separate first portion of the testbench by receiving and processing input data at its inputs to produce output data at its outputs, wherein inputs and outputs of the emulation resources are mapped to separate addresses within a memory address space;
• a transaction device connected to the packet routing network and connected to the emulation resources for supplying input, data to emulation resource's inputs and monitoring output data produced at the emulation resource's outputs;
• and
• a first computer connected to the packet routing network and running first emulation software emulating a second portion of the testbench by executing read instructions for reading input data from addresses of the memory addresses, processing the input data read from addresses of the memory space to produce output data and executing write instructions for writing output data it produces to addresses of the memory space,
• wherein when the first emulation software executes a write instruction for writing first data to a first memory space address to which an emulation resource input is mapped, the first computer sends a first packet conveying the first data to the transaction device via the packet routing network and the transaction device responds to the first packet by supplying the first data as input data to the emulation resource input mapped to the first memory space address.