Method and apparatus for emulating a processor
AssigneeLucent Technologies Inc.
InventorsHerbert Wayne Halcomb, Marlon Zbigniew Kasprzyk
Life of this patent
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Abstract
One or more processor operations are emulated in a programmable logic device (PLD) (205) that selectively mimics processor behavior by a program that downloads (505) one or more processor operations into the PLD (205). Each operation may be selected (501) and repeated (513) continuously without interruption from any other processor operation unless such interruption is desired to take place. In addition, the PLD (205) has an adjustable or variable clock speed that provides for the ability to select (507) and change (511) the clock speed under which the test circuit is exercised.
Claims17
An apparatus comprising:
- a programmable logic device, arranged and constructed to receive a program that programs at least one processor operation and a variable clock speed into the programmable logic device;
- at least one interface device through which the program and the variable clock speed are programmed into the programmable logic device;
- wherein the programmable logic device is arranged and constructed to adjust the variable clock speed during execution of the at least one processor operation;
- wherein the programmable logic device is arranged and constructed to emuate the at least one processor operation repeatedly without interruption from one or more cyclical processor operations other than the at least one operation of the processor.
A method comprising the steps of:
- selecting an operation that emulates at least one operation of a processor;
- downloading the operation into a programmable logic device;
- selecting a clock speed at which to operate the programmable logic device;
- programming the programmable logic device to operate at the clock speed;
- repeatedly testing the operation in combination with a circuit without waiting through processor operation cycles that do not provide the operation;
- adjusting the clock speed during the step of repeatedly testing the operation in combination with the circuit.
A computer-readable signal-bearing medium on which are recorded one or more executable processor instructions comprising:
- computer readable program code for downloading one or more processor operations into a programmable logic device;
- computer readable program code for selecting one of the one or more processor operations;
- computer readable program code for selecting a clock speed at which to operate the programmable logic device;
- computer readable program code for programming the programmable logic device to operate at the clock speed;
- computer readable program code for repeatedly executing the selected one of the one or more processor operations without waiting through one or more other processor operations of a precessor operation cycle that do not provide the selected one of the one or more processor operations;
- and
- computer readable program code for adjusting the clock speed while repeatedly executing the selected one of the one or more processor operations.
Dependencies are inferred from the claim text.