Device and method for synchronizing an asynchronous signal in synthesis and simulation of a clocked circuit

An apparatus for detecting undefined signal-time behavior in a clocked circuit comprising:

• a) an input for a first code describing a clocked circuit in a hardware description language;
• b) a first memory for storing said first code;
• c) a marking mechanism for marking asynchronous signals in said first code;
• d) a synthesis mechanism that produces a second code in a network list format from said first code and stores this in a second memory, a synchronization module being inserted at every marking;
• e) a timing simulator that implements a timing simulation at said second code for testing time behavior of signals of said clocked circuit, the test of the time behavior being selectively deactivated for each inserted synchronization module by adaptation in a simulation model of an appertaining synchronization module;
• f) a display for displaying occurring, undefined signal-time behavior;
• and
• g) a bus structure that connects said input, said first memory, said second memory, said marking mechanism, said display, said synthesis mechanism, and said timing simulator to one another.