Method for locating functional mistakes in digital circuit designs
OwnerZhe Liinventor
Life of this patent
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Abstract
This debugging method exhaustively analyzes the impact of any set of given interrelated signal values in a digital circuit on the circuit's ability to satisfy a set of functional expectations. It accomplishes this automatically by inspecting paths in a binary decision diagram representation of the logical relationship between the signal values in the circuit. As the result, it is able to list all combinations of desirable values on these given signals, and therefore it can conclusively identify which signals are irrelevant and which signals are always involved while other signals are involved under certain known conditions.
Claims20
A computer-implemented method for debugging a circuit design given a first set of at least one candidate branch, a second set of at least one correction probe, and a third set of at least zero restriction probe, comprising the steps of:
- obtaining said circuit design, said first set of at least one candidate branch, said second set of at least one correction probe, and said third set of at least zero restriction probe, whereby the existence of some functional mistake in the circuit design is clearly shown with definite boundaries;
- building a representation of the relationships among objects including said circuit design, said first set of at least one candidate branch, said second set of at least one correction probe, and said third set of at least zero restriction probe;
- and
- identifying combinations of behaviors at members of said first set of at least one candidate branch to make said circuit design satisfy the expectation expressed in said second set of at least one correction probe and said third set of at least zero restriction probe, whereby the information on the location of the functional mistake is derived.
Dependencies are inferred from the claim text.