Method of designing an initiator in an integrated circuit

A computer implemented method of designing an arbiter in an integrated circuit comprising initiators and targets, and an interconnect coupled to communicate packets between the initiators and targets, said arbiter being provided between said initiators and said interconnect, said method comprising the steps of:

• using an arbitration model having a plurality of different arbitration methods, wherein each arbitration method specifies whether the initiator is responsible for ensuring time based ordering of packets is handled, and selecting one of the plurality of arbitration methods available in said model;
• and
• producing a description of the integrated circuit using the selected one of the plurality of arbitration methods.

A computer implemented method of designing an arbiter in an integrated circuit comprising initiators and targets, and an interconnect coupled to communicate packets between the initiators and targets, said arbiter being provided between said initiators and said interconnect, said method comprising the steps of:

• using an arbitration model having a plurality of different arbitration methods, wherein each arbitration method specifies whether the initiator is responsible for ensuring time based ordering of packets is handled, and selecting one of the plurality of arbitration methods available in said model, wherein the method further comprises selecting whether a delay is to be provided after arbitration has been performed;
• and
• producing a description of the integrated circuit using the selected one of the arbitration methods and results of the selecting of whether a delay is to be provided after arbitration has been performed.

A computer implemented method of designing an arbiter in an integrated circuit comprising initiators and targets, and an interconnect coupled to communicate packets between the initiators and targets, said arbiter being provided between said targets and said interconnect, said method comprising the steps of

• using an arbitration model having a plurality of different arbitration methods, wherein each arbitration method specifies whether the initiator is responsible for ensuring time based ordering of packets is handled, and selecting one of the plurality of arbitration methods available in said model;
• and
• producing a description of the integrated circuit using output of the selected one of the arbitration methods.

A computer implemented method of designing an arbiter in an integrated circuit comprising initiators and targets, and an interconnect coupled to communicate packets between the initiators and targets, said arbiter being provided between said targets and said interconnect, said method comprising the steps of:

• using an arbitration model having a plurality of different arbitration methods, wherein each arbitration method specifies whether the initiator is responsible for ensuring time based ordering of packets is handled, and selecting one of the plurality of arbitration methods available in said model, wherein the method further comprises selecting if a delay is to be provided after arbitration has been performed;
• and
• producing a description of the integrated circuit using the selected one of the arbitration methods and results of the selecting of whether a delay is to be provided after arbitration has been performed.

A model of an initiator implemented in a computer to be used in designing an integrated circuit in which an initiator is arranged to send packet-format requests to one or more targets via an interconnect, said model embodied as a plurality of parameters stored in a computer file, said model comprising:

• an address decode stage running on the computer for identifying the target for which a given message is intended;
• and
• a dependency stage running on the computer for determining the allowability of a request, the operation of said dependency stage being selectable, said dependency stage being such that the model supports an arrangement where the initiator or the interconnect is responsible for maintaining the order of packet-format responses from a target to the requests.

A computer implemented model of a target to be used in designing an integrated circuit in which one or more initiators are arranged to send packet-format requests to a target and the target is arranged to send packet-format responses to the requests via an interconnect, said model embodied as a plurality of parameters stored in a computer file, said model comprising:

• a locking stage for causing a computer to permit locked transactions to occur if required;
• and
• a decode state for causing the computer to decode information stored in a first queue into an address for the response.