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US 7,072,814 B1Granted
Evolutionary technique for automated synthesis of electronic circuits
AssigneeThe United States of America as represented by the Administrator of the National Aeronautics and Space Administration
InventorAdrian Stoica
Life of this patent
Estimating the term…
Abstract
A method of evolving a circuit uses a heterogenous mix of models of both high and low levels of resolution.
Claims19
A method of designing an electronic circuit from plural candidate circuits, comprising:
- assigning each one of a plurality of configurable circuit models of different levels of model resolutions to different individual ones of at least a subset of said plural candidate circuits;
- producing plural simulation models for each one of at least said subset of said candidate circuits by configuring each configurable model in accordance with the one candidate circuit, whereby to produce a plurality of simulation models corresponding to different levels of model resolutions;
- obtaining from each simulation model a fitness function of the corresponding candidate circuit;
- ranking said candidate circuits in accordance with said fitness functions;
- changing assignments of candidate circuits among said configurable circuit models;
- and
- repeating the steps of producing, obtaining and ranking, whereby to perform them in successive iterations.
4 more elements
A method of designing an electronic circuit from plural candidate circuits, comprising:
- assigning every one of a plurality of configurable circuit models of different levels of model resolutions to each one of at least a subset of said plural candidate circuits;
- producing plural simulation models for each one of at least said subset of said candidate circuits by configuring each configurable model in accordance with the one candidate circuit, whereby to produce a plurality of simulation models for each candidate circuit;
- obtaining from the plurality of simulation models of each candidate circuit a plurality fitness functions of the corresponding candidate circuit, and combining said plurality of fitness functions into a single fitness function of the one candidate circuit;
- ranking said candidate circuits in accordance with their fitness functions.
1 more element
A method of designing an elecontroic circuit comprising modeling plural candidate circuits at different levels of resolution over a plurality of iterations.
Dependencies are inferred from the claim text.