Semiconductor memory apparatus

A semiconductor memory apparatus comprising:

• two bank areas having one-port memories capable of performing writing and reading only with separate timings and capable of selecting one of an upper side bit string and a lower side bit string of a data bus by the logic of writing control signals and writing data;
• a writing control circuit configured to write data into said one-port memories in one bank area of said two bank areas;
• and
• a reading control circuit configured to read data from said one-port memories in the other bank area and zero-clearing memory areas from which data has been read while said writing control circuit is writing data.