Clock timing recovery using arbitrary sampling frequency

Apparatus for regenerating a bit timing signal from an encoded digital signal in a receiver using a predetermined sample rate Fs, said apparatus comprising:

• an input pulse generator coupled to said encoded digital signal and generating input pulse signals triggered by said encoded digital signal;
• a clock generator providing a clock count signal having a variable clock period according to cyclical counting of said clock count signal up to a count value S at said predetermined sample rate, said count value alternating between an upper value Su, and a lower value Sl so that said variable clock period has an average length substantially equal to a data bit period of said encoded digital signal;
• and
• a synchronizer coupled to said input pulse generator and to said clock generator for 1) counting said input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal to reset said clock count signal if said pulse count is greater than a pulse threshold and said sample count is greater than a sample threshold.