Method and apparatus for generating multi-level reference voltage in systems using equalization or crosstalk cancellation
AssigneeRambus Inc.
InventorsJared Zerbe, Carl Werner
Life of this patent
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Abstract
A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.
Claims15
A system comprising:
- a. a multi-PAM output driver having a plurality of current-control ports;
- b. a current-calibration circuit coupled to each of the current-control ports, the current-calibration circuit including a first, second, and third reference-voltage nodes;
- and
- c. a multi-level voltage generator including:
- i. a voltage divider having first, second, third, and fourth resistors coupled in series to divide a reference voltage into a first multi-PAM reference voltage between the first and second resistors and coupled to the first reference-voltage node, a second multi-PAM reference voltage between the second and third resistors and coupled to the second reference-voltage node, and a third multi-PAM reference voltage between the third and fourth resistors and coupled to the third reference-voltage node;
- and
- ii. an active current source having a current-handling terminal and a current-control terminal, wherein the current-handling terminal is coupled between two of the first, second, third, and fourth resistors.
A current-calibration circuitry for a multi-PAM output driver, the current-calibration circuitry comprising:
- a. a current-calibration circuit including a first, second, and third reference-voltage nodes adapted to receive respective relatively high, medium, and low reference voltages;
- and
- b. a multi-level voltage generator adapted to produce the high, medium, and low reference voltages, the voltage generator including:
- i. first and second voltage supply pins providing a reference voltage;
- ii. a voltage divider having first, second, and third multi-PAM reference terminals, the voltage divider dividing the reference voltage into a plurality of multi-PAM references, including a first multi-PAM reference voltage on the first multi-PAM reference terminal, a second multi-PAM reference voltage on the second multi-PAM reference terminal, and a third multi-PAM reference voltage on the third multi-PAM reference terminal;
- and
- iii. an active current source drawing current from the first multi-PAM reference terminal to reduce the first multi-PAM reference voltage.
A method for calibrating a multi-PAM output driver adapted to cause an output signal to transition between a plurality of logic states, the method comprising:
- a. dividing a reference voltage into a plurality of multi-PAM reference voltages on respective multi-PAM reference-voltage nodes;
- and
- b. shifting the logic states to allow equalization signals to overdrive transitions between the logic states, wherein shifting the logic states includes shifting the multi-PAM reference voltages by drawing an offset current from one of the multi-PAM reference-voltage nodes.
Dependencies are inferred from the claim text.