Flexible buffering scheme for multi-rate SIMD processor
AssigneeCiena Corporation
InventorsFred Stacey, Christian Bourget, Yatish Kumar
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Abstract
A single instruction, multiple data (SIMD) architecture for controlling the processing of plurality of data streams in a digital subscriber line (DSL) system has a memory for storing the data from the channels, a processor operatively coupled with the memory for processing data from the data streams, and a controller for controlling the processor. Storing the data in the memory de-couples the operating rate of the processor and the operating rate of the data streams.
Claims15
A single instruction, multiple data (SIMD) controller for processing a plurality of data streams in a digital subscriber line (DSL) system, comprising:
- a plurality of circular buffer circuits that store data from said plurality of data streams having independent data rates;
- a plurality of address generation circuits that access said data stored in said plurality of circular buffer circuits;
- a plurality of processor circuits that process said data accessed by said plurality of address generation circuits;
- and
- a program control unit that controls said plurality of processor circuits with an instruction.
A method of processing a plurality of data streams in a digital subscriber line (DSL) system, comprising the acts of:
- calculating a plurality of input addresses for said plurality of data streams based on a plurality of input base addresses and a plurality of input offset addresses;
- storing a plurality of data from said plurality of data streams according to said plurality of input addresses;
- calculating a plurality of processor addresses for the stored plurality of data based on a plurality of processor base addresses and a plurality of processor offset addresses;
- processing, using a single instruction, the stored plurality of data according to said plurality of processor addresses;
- calculating a plurality of output addresses for the processed plurality of data based on a plurality of output base addresses and a plurality of output offset addresses;
- outputting the processed plurality of data according to said plurality of output addresses;
- and
- updating said plurality of input base addresses, said plurality of processor base addresses, and said plurality of output base addresses.
A single instruction, multi data (SIMD) architecture for controlling the processing of plurality of data streams, comprising:
- a memory that stores data from said plurality of data streams received from a plurality of channels;
- a processor, operatively coupled with said memory, that processes said data from said plurality of data streams;
- and
- a controller that controls said processor, wherein storing said data in said memory de-couples a first operating rate of said processor and a second operating rate of said plurality of channels.
A method of controlling processing of multiple data streams in a single instruction, multi data (SIMD) architecture, comprising the steps of:
- storing data from said multiple data streams in a memory as said data is received;
- at regular intervals, determining whether all of said data has been received;
- providing a signal indicating that all of said data has been received;
- using said signal to determine which of said data to process;
- and
- processing said data in accordance with said signal.
Dependencies are inferred from the claim text.