# US 7,072,242 B2 · Semiconductor integrated circuit device

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- Number: US 7,072,242 B2
- Document ID: US7072242B2
- Status: Granted
- Kind: B2
- Application number: 10/965,845
- Filed: 2004-10-18
- Published: 2005-03-10
- Granted: 2006-07-04
- Earliest claimed: 1999-08-30
- Assignees: Renesas Technology Corp.
- Inventors: Yuichi Okuda; Masaru Kokubo; Yoshinobu Nakagome; Hideharu Yahata; Hiroki Miyashita
- Web page: https://patentgrep.com/patent/US7072242B2

## CPC

- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/12005: {comprising voltage or current generators}
- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03L 7/0898: {the source or sink current values being variable (H03L7/0896 takes precedence)}
- H03L 7/1072: {by changing characteristics of the charge pump, e.g. changing the gain}
- H03L 2207/14: Preventing false-lock or pseudo-lock of the PLL
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

## Claims

### Claim 1

A semiconductor integrated circuit device which includes:
a variable delay circuit which delays clock signals input through an external terminal; and
a control circuit which compares the phase of a delay signal that has passed through the variable delay circuit with the phase of one of the clock signals using a phase comparator circuit, and for forming internal clock signals by controlling the delay time of the variable delay circuit, so that the phase difference decreases;
wherein the control circuit controls the variable delay circuit so as to return the delay amount in the reverse direction when the variable delay time has exceeded a target value, and
wherein the amount of change in the delay time of the variable delay circuit is nearly constant for every phase comparing operation of the phase comparator circuit.

### Claim 2

A semiconductor integrated circuit device which includes:
a variable delay circuit which delays clock signals input through an external terminal; and
a control circuit which compares the phase of a delay signal that has passed through the variable delay circuit with the phase of one of the clock signals using a phase comparator circuit, and for forming internal clock signals by controlling the delay time of the variable delay circuit so that the phase difference decreases;
wherein the control circuit controls the variable delay circuit so as to return the delay amount in the reverse direction when the variable delay time has exceeded a target value, and
wherein the amount of change in the delay time of the variable delay circuit varies for every phase comparing operation of the phase comparator circuit depending upon operation conditions.

### Claim 3 (depends on 2)

A semiconductor integrated circuit device according to claim 2,
wherein the operation conditions include a first period which is from the beginning of operation of a clock-generating circuit until the target value is exceeded and a second period in which the delay time becomes smaller than the target value after the first period,
wherein the amount of change in the delay time of the variable delay circuit is set to be large during the first period,
wherein the amount of change in the delay time of the variable delay circuit is set to be smaller than the amount of change in the delay time in the first period during the second period, and
wherein the amount of change in the delay time of the variable delay circuit is set to be smaller than that in the second period after the second period.

### Claim 4 (depends on 2)

A semiconductor integrated circuit device according to claim 2,
wherein the amount of change in the delay time of the variable delay circuit decreases every time when the delay time of the variable delay circuit exceeds the target value within an extent in which a phase-synchronizing operation is not lost.

### Claim 5 (depends on 2)

A semiconductor integrated circuit device according to claim 2,
wherein the phase comparator circuit is constituted by a flip-flop circuit which is served with one of the clock signals and the delay signal,
wherein the phase comparator circuit forms a phase comparison signal in response to the phase difference, and
wherein the control circuit includes a circuit that forms pulse signals for flowing a charge-up current or a discharge current in response to the phase comparison signal to a charge pump circuit included in the variable delay circuit.

### Claim 6 (depends on 5)

A semiconductor integrated circuit device according to claim 5,
wherein the amount of delay time of the variable delay circuit can be varied in accordance with the pulse signals and the current flowing into the charge pump circuit so that the amount of delay time varies depending upon the pulse signals.

### Claim 7 (depends on 1)

A semiconductor integrated circuit device according to claim 1,
wherein the phase comparator circuit is constituted by a flip-flop circuit which is served with the input clock signals and the internal clock signals through data terminals and clock terminals, and forms a phase comparison signal of a high level or a low level in response to the phase difference, and the control circuit includes a circuit that forms a pulse signal for flowing a charge-up current or a discharge current to a charge pump circuit in response to the phase comparison signal.

### Claim 8 (depends on 2)

A semiconductor integrated circuit device according to claim 2,
wherein the phase comparator circuit is constituted by a flip-flop circuit which is served with the input clock signals and the internal clock signals through data terminals and clock terminals, and forms a phase comparison signal of a high level or a low level in response to the phase difference, and the control circuit includes a circuit that forms a pulse signal for flowing a charge-up current or a discharge current to a charge pump circuit in response to the phase comparison signal.

### Claim 9 (depends on 3)

A semiconductor integrated circuit device according to claim 3,
wherein the phase comparator circuit is constituted by a flip-flop circuit which is served with the input clock signals and the internal clock signals through data terminals and clock terminals, and forms a phase comparison signal of a high level or a low level in response to the phase difference, and the control circuit includes a circuit that forms a pulse signal for flowing a charge-up current or a discharge current to a charge pump circuit in response to the phase comparison signal.

### Claim 10 (depends on 4)

A semiconductor integrated circuit device according to claim 4,
wherein the phase comparator circuit is constituted by a flip-flop circuit which is served with the input clock signals and the internal clock signals through data terminals and clock terminals, and forms a phase comparison signal of a high level or a low level in response to the phase difference, and the control circuit includes a circuit that forms a pulse signal for flowing a charge-up current or a discharge current to a charge pump circuit in response to the phase comparison signal.