Method and device for varying an active duty cycle of a wordline

A method of testing a memory cell within a semiconductor memory having a test mode interface, comprising:

• activating the test mode interface of the semiconductor memory;
• entering information through the test mode interface to set a variable autoprecharge timing measured between a start of an activation interval of a wordline and a start of a precharge interval to a first value;
• switching a bitline connected to the memory cell to a first logic level;
• providing an external precharge signal to the semiconductor memory;
• activating the wordline to write the memory cell according to the first logic level, wherein an ending point of the active duty cycle of the wordline is determined at least partly by the external precharge signal;
• providing a signal to select the autoprecharge timing;
• switching the bitline to a second logic level;
• activating the wordline to write the memory cell according to the second logic level, wherein the length of the wordline activation interval is determined by the first value;
• and
• reading the contents of the memory cell to determine whether the memory cell successfully retains the second logic level.

A semiconductor memory operable in at least a test mode, comprising:

• a memory array including a plurality of memory cells accessible through a plurality of respective wordlines and a plurality of respective bitlines;
• a row decoder driver operable to activate one wordline of the plurality of wordlines at a first point in time determined in relation to a first signal and to deactivate the wordline at a second point in time determined in relation to a second signal;
• precharge circuit operable to precharge one of the plurality of bitlines at a third point in time, the third point in time occurring no sooner than the second point in time;
• and
• a variable length delay circuit operable to output the second signal at a delayed timing, delayed in relation to the first signal and occurring after the first signal, the delayed timing having a controllably variable length.