Nonvolatile memory system

A nonvolatile memory system comprising:

• one or more semiconductor memories;
• and
• an information processor for reading data stored in said one or more semiconductor memories, giving a data writing operation instruction or performing a predetermined process on the basis of an operation program,
• wherein said information processor includes:
• a power supply voltage unit for generating an internal power supply voltage from an external power supply voltage and supplying the internal power supply voltage to said one or more semiconductor memories and said information processor;
• a first voltage monitoring unit for outputting a power-on-reset signal when the internal power supply voltage generated by said power supply voltage unit reaches a first voltage level;
• and
• a second voltage monitoring unit for outputting an emergency stop signal when the external power supply voltage reaches a second voltage level, and
• wherein when the emergency stop signal output from said second voltage monitoring unit is received, said information processor stops an operation being performed and enters a no-response state in which no response is given to a process request from outside, and when the power-on-reset signal output from said first voltage monitoring unit is received, said information processor performs a resetting process.

A nonvolatile memory system comprising:

• one or more semiconductor memories;
• and
• an information processor for reading data stored in said one or more semiconductor memories, giving a data writing operation instruction or performing a predetermined process on the basis of an operation program,
• wherein said information processor includes:
• a power supplying unit for supplying an auxiliary power supply voltage;
• a power supply switching unit for outputting an emergency stop signal when an external power supply voltage reaches a first voltage level, switching said external power supply voltage to the power supply voltage of said power supplying unit and supplying the power supply voltage to said one or more semiconductor and said information processor;
• and
• a first voltage monitoring unit for outputting a power-on-reset signal when said external power supply voltage reaches a second voltage level,
• wherein when the emergency stop signal output from said power supply switching unit is received, said information processor stops an operation being performed and enters a no-response state in which no response is given to a process request from outside, and when the power-on-reset signal which is output from said first voltage monitoring unit is received, said information processor performs a resetting process.

A nonvolatile memory system comprising:

• one or more semiconductor memories;
• and
• an information processor for reading data stored in said one or more semiconductor memories, giving a data writing operation instruction or performing a predetermined process on the basis of an operation program,
• wherein said information processor has a transfer mode storing unit for storing transfer function setting data for setting a transfer mode of error data, refers to the transfer function setting data in said transfer mode storing unit in a data transfer process at the time of a read operation or a write operation and, when an error data transfer function of said transfer function setting data is set to be valid, executes a transfer process even if transfer data includes error data.

A nonvolatile memory system comprising:

• one or more semiconductor memories;
• and
• an information processor for reading data from said one or more semiconductor memories, giving a data writing operation instruction or performing a predetermined process on the basis of an operation program,
• wherein an error determining unit is provided for determining whether an error is included in the data read from said one or more semiconductor memories at a time of reading the data from said one or more semiconductor memories, and
• wherein the nonvolatile memory system has a first reading operation for determining whether an error is included in the data read from said one or more semiconductor memories and outputting the data, and a second reading operation for outputting the data read from said one or more semiconductor memories without determining whether an error is included.