Reduced power registered memory module and method

A memory module, comprising:

• a receiver circuit receiving a plurality of signals at respective input terminals, the receiver circuit inputting the signals responsive to a transition of an internal clock signal applied to a clock terminal when an enable signal is active, the receiver circuit having output terminals to which the input signals are coupled when the enable signal is active;
• a plurality of memory devices coupled to the output terminals of the receiver circuit, each of the memory devices being selected by a respective select signal being active;
• and
• a logic circuit receiving the select signals for the memory devices and applying the enable signal to the receiver circuit, the logic circuit being structured to make the enable signal active responsive to any of the select signals being active and to make the enable signal inactive response to none of the select signals being active.

A memory module, comprising:

• a receiver circuit receiving a plurality of signals at respective input terminals, the receiver circuit inputting the signals responsive to a transition of an internal clock signal applied to a clock terminal when an enable signal is active, the receiver circuit having output terminals to which the input signals are coupled when the enable signal is active;
• a plurality of memory devices coupled to the output terminals of the receiver circuit;
• and
• a logic circuit applying the enable signal to the receiver circuit, the logic circuit being structured to make the enable signal active responsive to one of the memory devices in the memory module being accessed.

A computer system, comprising:

• a central processing unit (“CPU”);
• a system controller coupled to the CPU;
• an input device coupled to the CPU through the system controller;
• an output device coupled to the CPU through the system controller;
• a storage device coupled to the CPU through the system controller;
• and
• at least one registered memory module coupled to the CPU through the system controller, the at least one registered memory module comprising:
• a register receiving a plurality of input signals at respective input terminals, the register storing the input signals responsive to a transition of an internal clock signal applied to a clock terminal when an enable signal is active, the register having output terminals to which the stored input signals are coupled;
• a plurality of memory devices coupled to the output terminals of the register;
• and
• a logic circuit applying the enable signal to the register, the logic circuit being structured to make the enable signal active responsive to one of the memory devices in the memory module being accessed.

A computer system, comprising:

• a central processing unit (“CPU”);
• a system controller coupled to the CPU;
• an input device coupled to the CPU through the system controller;
• an output device coupled to the CPU through the system controller;
• a storage device coupled to the CPU through the system controller;
• and
• at least one memory module coupled to the CPU through the system controller, the at least one memory module comprising:
• a receiver receiving a plurality of input signals at respective input terminals, the receiver coupling the input signals to respective output terminals responsive to a transition of an internal clock signal applied to a clock terminal when an enable signal is active;
• a plurality of memory devices coupled to the output terminals of the receiver, each of the memory devices being selected by a respective select signal being active;
• and
• a logic circuit receiving the select signals for the memory devices and applying the enable signal to the register, the logic circuit being structured to make the enable signal active responsive to any of the select signals being active and to make the enable signal inactive response to none of the select signals being active.

A method of accessing a plurality of memory devices coupled to a receiver that receives a plurality of input signals, the method comprising:

• determining whether or not a memory access is directed to any of the memory devices;
• periodically coupling the input signals to respective output terminals of the receiver responsive to determining that the memory access is directed to any of the memory devices;
• and
• refraining from periodically coupling the input signals to respective output terminals of the receiver responsive to determining that the memory access is not directed to any of the memory devices;
• and
• coupling the input signals from the output terminals to at least one of the memory devices.

In a memory module having an input circuit for performing an operation on input signals responsive to a clock signal and coupling signals resulting from the input signals to a plurality of memory devices in the module, a method of reducing the power consumed by the memory module, comprising:

• determining whether or not a memory access is directed to any of the memory devices in the module;
• enabling the input circuit to perform the operation on the input signals responsive to determining that the memory access is directed to any of the memory devices;
• and
• disabling the input circuit from perform the operation on the input signals responsive to determining that the memory access is not directed to any of the memory devices.