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US 7,072,228 B2Granted
Semiconductor memory device with improved precharge timing
AssigneeKabushiki Kaisha Toshiba
InventorMakoto Takahashi
Life of this patent
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Abstract
A memory cell array has a plurality of memory cells arranged in row and columns, and bit lines and word lines connected to the memory cells. A command buffer circuit receives at least an active signal to activate one of the rows, and a clock signal, and generates an internal precharge signal to precharge the bit lines based on the active signal.
Claims9
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns, and bit lines and word lines connected to the memory cells;
- a command buffer circuit, which receives at least an active signal to activate one of the rows, and a clock signal, the command buffer circuit generating an internal precharge signal to precharge the bit lines based on the active signal;
- a latch circuit to which the clock signal and the active signal are supplied, the latch circuit latching the active signal in response to the clock signal;
- a logic circuit to which the active signal latched by the latch circuit and the clock signal are supplied, the logic circuit generating the internal precharge signal;
- and
- a delay circuit which delays the internal precharge signal supplied from the logic circuit, and generates an internal active signal.
3 more elements
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns, and bit lines and word lines connected to the memory cells;
- a command buffer circuit, which receives at least an active signal to activate one of the rows, and a clock signal, the command buffer circuit generating an internal precharge signal to precharge the bit lines based on the active signal;
- a detection circuit which monitors a potential of a word line, and detects a precharge period of said word line;
- and
- a logic circuit which activates a word line of the word lines, in response to the active signal and a detection output signal of the detection circuit.
2 more elements
A semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged in rows and columns, and bit lines and word lines connected to the memory cells;
- a command buffer circuit, which receives at least an active signal to activate one of the rows, and a clock signal, the command buffer circuit generating an internal active signal based on the active signal;
- a control circuit which generates an internal precharge signal to precharge the bit lines in response to the active signal outputted from the command buffer circuit, the control circuit controls a time in which one of the word lines is kept selected;
- wherein the command buffer circuit further includes:
- a latch circuit to which the clock signal and the active signal are supplied, the latch circuit latching the active signal in response to the clock signal;
- a logic circuit to which the active signal latched by the latch circuit and the clock signal are supplied, the logic circuit generating the internal precharge signal;
- and
- a delay circuit which delays the internal precharge signal supplied from the logic circuit, and generates an internal active signal.
5 more elements
Dependencies are inferred from the claim text.