Method and apparatus for operating a non-volatile memory array
AssigneeMacronix International Co., Ltd.
InventorChih Chieh Yeh
Life of this patent
Estimating the term…
Abstract
An array of memory cells with a charge trapping structure coupled in series is read, by measuring current that flows between the body region of the selected memory cell and the contact region of the selected memory cell. The charge storage state of the charge trapping structure affects the measured current.
Claims56
A method of operating an array of memory cells arranged in rows and columns, each or the memory cells comprising a body region, a contact region, a bottom dielectric, a charge trapping structure, and a top dielectric, wherein the contact region of memory cells in a particular column of the columns of memory cells is electrically coupled to a particular bit line of a plurality of bit lines arranged in columns, and the top dielectric of memory cells in a particular row of the rows is electrically coupled to a particular word line of a plurality of word lines arranged in rows, the method comprising:
- applying a first bias arrangement to determine the charge storage state of the charge trapping structure of at least a selected memory cell, wherein the first bias arrangement applies a first voltage to the particular bit line coupled to the contact region of the selected memory cell and a second voltage to the particular word line electrically coupled to the top dielectric of the selected memory cell;
- and
- measuring current flowing between the particular bit line and the body region of the selected memory cell to determine the charge storage state of the charge trapping structure of the selected memory cell.
A nonvolatile memory, comprising:
- a plurality of bit lines;
- a memory array including a plurality of memory cells arranged in rows and columns, each memory cell including:
- a body region;
- a contact region coupled to the body region, wherein the contact region of memory cells in a particular column of the columns is electrically coupled to a corresponding bit line of the plurality of bit lines;
- a bottom dielectric coupled to the body region;
- a charge trapping structure coupled to the bottom dielectric having a charge storage state;
- and
- a top dielectric coupled to the charge trapping structure;
- a plurality of word lines coupled to the top dielectrics of the plurality of memory cells, each word line of the plurality of word lines providing voltage as a gate for memory cells of a particular row of the rows;
- and
- logic coupled to the plurality of bit lines and the plurality of word lines, the logic applying a first bias arrangement to determine the charge storage state of the charge trapping structure of at least a selected memory cell, and the logic measuring current flowing in response to the first biasing arrangement to determine the charge storage state of the charge trapping structure of the selected memory cell, the current flowing between the body region of the selected memory cell and the contact region of the selected memory cell.
A method of manufacturing nonvolatile memory, comprising:
- providing a semiconductor substrate;
- providing a plurality of bit lines;
- providing a memory array including a plurality of memory cells arranged in rows and columns, each memory cell including:
- a body region;
- a contact region coupled to the body region, wherein the contact region of memory cells in a particular column of the columns is electrically coupled to a corresponding bit line of the plurality of bit lines;
- a bottom dielectric coupled to the body region;
- a charge trapping structure coupled to the bottom dielectric having a charge storage state;
- and
- a top dielectric coupled to the charge trapping structure;
- providing a plurality of word lines coupled to the top dielectrics of the plurality of memory cells, each word line of the plurality of word lines providing voltage as a gate for memory cells of a particular row of the rows;
- and
- providing logic coupled to the plurality of bit lines and the plurality of word lines, the logic applying a first bias arrangement to determine the charge storage state of the charge trapping structure of at least a selected memory cell, and the logic measuring current flowing in response to the first biasing arrangement to determine the charge storage state of the charge trapping structure of the selected memory cell, the current flowing between the body region of the selected memory cell and the contact region of the selected memory cell.
Dependencies are inferred from the claim text.