Array structure of two-transistor cells with merged floating gates for byte erase and re-write if disturbed algorithm
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorYeu-Der Chih
Life of this patent
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Abstract
Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.
Claims23
A memory array utilizing cells with one split gate transistor, comprising:
- an array of one transistor split gate cells arranged into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells,
- a split source line connected to said even and odd addressed cells,
- said first row being connected with a first word line and said second row being connected with a second word line, and
- said cells in one of said columns being connected to a bit line
- wherein each of said first and second word lines is divided into word line segments.
A memory array utilizing cells with two split gate transistors, comprising:
- an array of two transistor split gate cells arranged into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells,
- a split source line connected to said even and odd addressed cells,
- said first row being connected with a first word line and said second row being connected with a second word line, and
- said cells in one of said columns being connected to a program bit line and a read bit line.
A memory array utilizing cells with three split gate transistors, comprising:
- an array of cells containing three split gate transistors arranged into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells,
- a floating gate shared between a first and a second split gate transistor of said three split gate transistors,
- a source line shared between said even and odd addressed cells,
- said first row being connected with a first word line and said second row being connected with a second word line, and
- said cells in one of said columns being connected with a first program bit line, a second program bit line and a read bit line.
A memory array utilizing cells with two split gate transistors, comprising:
- an array of cells containing two split gate transistors arranged into rows and columns in which even addressed cells are located in a first row of cells and odd addressed cells are located in a second row of cells,
- a floating gate shared between a first and a second split gate transistor of said two split gate transistors,
- a source line shared between said even and odd addressed cells,
- said first row being connected with a first word line and said second row being connected with a second word line,
- said cells in one of said columns being connected with a first program bit line, a second program bit line and a read bit line.
A memory array containing cells with two split gate transistors, comprising:
- an array of cells containing two split gate transistors arranged in rows and columns,
- a floating gate shared between a first and a second split gate transistor of said two split gate transistors,
- means for increasing the threshold voltage of said first split gate transistor,
- a source line shared between said even and odd addressed cells,
- said first row being connected with a first word line and said second row being connected with a second word line,
- said cells in one of said columns being connected with a program bit line and a read bit line.
Dependencies are inferred from the claim text.