NROM flash memory cell with integrated DRAM
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides multiple modes of operation including a DRAM mode using the capacitor and a non-volatile random access memory mode using the NROM transistor. The device is comprised of two source/drain regions between which a gate insulator layer is formed. A control gate, coupled to a word line, is formed on top of the gate insulator. The DRAM capacitor is coupled to one of the source/drain regions while the second source/drain region is coupled to a bit line that is eventually coupled to a sense amplifier for reading the state or states of the memory device.
Claims17
A method for programming data from a dynamic random access memory (DRAM) to a non-volatile, nitride read only memory (NROM) transistor in a memory device, the DRAM coupled to first source/drain region of the transistor, the transistor having a control gate coupled to a word line and a second source/drain region coupled to a bit line, the method comprising:
- determining whether the memory device is in a repressed mode or a dynamic mode;
- applying a negative voltage to the word line for a predetermined period of time;
- and removing the negative voltage.
A method for programming a memory device comprising a dynamic random access memory (DRAM) coupled to a non-volatile, nitride read only memory (NROM) transistor with a nitride trapping layer, the DRAM coupled to first source/drain region of the transistor, the transistor having a control gate coupled to a word line and a second source/drain region coupled to a bit line, the method comprising:
- biasing the second source/drain region at −½ V;
- applying a first potential to the word line to write data into the DRAM;
- and
- applying a second potential to the word line to write data into the NROM transistor, the second potential different from the first potential.
A memory device comprising:
- a memory array having a plurality of flash memory cells with integrated DRAM, each memory cell comprising a dynamic random access memory capacitor that provides a dynamic mode of operation and a nitride read only memory (NROM) transistor that provides a repressed non-volatile random access memory mode of operation, the NROM transistor coupled between the capacitor and a data line and acting as a transfer gate for the capacitor, the transistor comprising a control gate and a data storage layer;
- and
- control circuitry that is adapted to execute a programming operation of the memory array, the programming operation comprising detecting a power-down condition of the memory device and applying a negative voltage to the word line for a predetermined period of time.
An electronic system comprising:
- a processor that generates control signals;
- and
- a memory device coupled to the processor and operating in response to the control signals, the device comprising:
- a memory array having a plurality of flash memory cells with integrated DRAM, each memory cell comprising a dynamic random access memory capacitor that provides a dynamic mode of operation and a nitride read only memory (NROM) transistor that provides a repressed non-volatile random access memory mode of operation, the NROM transistor coupled between the capacitor and a data line and acting as a transfer gate for the capacitor, the transistor comprising a control gate and a data storage layer;
- and
- control circuitry that is adapted to execute a programming operation comprising applying a negative voltage to the word line for a predetermined period of time to program data stored in the DRAM into the NROM transistor and removing the negative voltage after the predetermined period of time such that the NROM transistor is used as a shadow memory for the dynamic random access memory canacitor and the data from the capacitor is written to the NROM transistor upon a power-down condition of the system.
Dependencies are inferred from the claim text.