Memory array
AssigneeApplied Intellectual Properties Co., Ltd.
InventorErik S. Jeng
Life of this patent
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Abstract
A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, and a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.
Claims27
A memory array, comprising:
- a plurality of word lines;
- a plurality of first source/drain lines;
- a plurality of second source/drain lines;
- and
- a plurality of memory units, comprising:
- a gate electrode, coupled to one of the word lines;
- a gate dielectric layer laid below the gate electrode;
- a first source/drain region, coupled to one of the first source/drain lines or first bit lines, further comprising a first multi-layer dielectric spacer formed between the first source/drain region and the gate electrode to store electrons or electric charges;
- and
- a second source/drain region, coupled to one of the second source/drain lines or second bit lines, further comprising a second multi-layer dielectric spacer formed between the second source/drain region and the gate electrode to store electrons or electric charges;
- a metal-semiconductor compound layer formed over the gate electrode, first source/drain region and second source/drain region;
- a semiconductor channel formed between said first source/drain region and second source/drain region.
A memory array, comprising:
- a plurality of word lines;
- a plurality of first source/drain lines;
- a plurality of second source/drain lines;
- and
- a plurality of memory units, comprising:
- a gate electrode, coupled to one of the word lines;
- a gate dielectric layer laid below the gate electrode;
- a first source/drain region, coupled to one of the first source/drain lines or first bit lines;
- and
- a second source/drain region, coupled to one of the second source/drain lines or second bit lines, further comprising a programmable source/drain extended doped area formed between the gate electrode and the first or second source/drain region for storing or keeping electric information;
- a metal-semiconductor compound layer formed over the gate electrode, first source/drain region and second source/drain region;
- a semiconductor channel formed between said first source/drain region and second source/drain region.
A memory array, comprising:
- a plurality of word lines;
- a plurality of first source/drain lines;
- a plurality of second source/drain lines;
- and
- a plurality of memory units, comprising:
- a gate electrode, coupled to one of the word lines;
- a dielectric spacer formed on the sidewalls of said gate electrode;
- a gate dielectric layer laid below the gate electrode;
- a first source/drain region, coupled to one of the first source/drain lines or first bit lines;
- and
- a second source/drain region, coupled to one of the second source/drain lines or second bit lines, further comprising an anti-fuse dielectric formed between the gate electrode and the first or second source/drain region;
- a metal-semiconductor compound layer formed over the gate electrode, first source/drain region and second source/drain region;
- a semiconductor channel formed between said first source/drain region and second source/drain region.
Dependencies are inferred from the claim text.