Floating-body DRAM with two-phase write
AssigneeIntel Corporation
InventorsStephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
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Abstract
A row of floating-body single transistor memory cells is written to in two phases.
Claims23
A method comprising writing data to floating-body memory cells in two phases, wherein each of the two phases utilizes a different word line voltage on a selected word line, and at least one of the two phases utilizes a different word line voltage on an unselected word line.
A method comprising:
- providing a first voltage on a selected word line coupled to a plurality of memory cells;
- writing “0” to at least one of the plurality of memory cells;
- providing a second voltage on the selected word line;
- increasing a voltage on unselected word lines;
- and
- writing “1” to at least one of the plurality of memory cells.
An apparatus comprising:
- a plurality of rows of memory cells;
- and
- a plurality of word line drivers, wherein each of the plurality of word line drivers is coupled to one of the plurality of rows of memory cells, the word line drivers to generate a first voltage when holding the state of the memory cells, a second voltage on a selected word line when writing a “0,” a third voltage on the selected word line when writing a “1,” and a fourth voltage on unselected word lines when writing a “1,” wherein the fourth voltage is greater than the first voltage.
A memory device comprising:
- floating-body single transistor memory cells;
- and
- a plurality of word line drivers coupled to the floating-body single transistor memory cells to increase a voltage on unselected word lines during a memory write cycle in which selected ones of the floating-body single transistor memory cells have their bodies charged.
An electronic system comprising:
- an antenna;
- a first integrated circuit coupled to the antenna;
- and
- a second integrated circuit including a memory device, the memory device comprising floating-body single transistor memory cells;
- and a plurality of word line drivers coupled to the floating-body single transistor memory cells to increase a voltage on unselected word lines during a memory write cycle in which selected ones of the floating-body single transistor memory cells have their bodies charged.
A method comprising increasing a voltage on unselected word lines during a memory device write cycle in which selected floating body transistors have their bodies charged.
Dependencies are inferred from the claim text.