Apparatus for optimizing processor clock frequency in a hard disk drive to minimize power consumption while maximizing performance

A disk drive system comprising:

• a rotatable disk containing magnetic media with data recordable in defined tracks;
• a transducer;
• an actuator arm that supports the transducer;
• a voice control motor (VCM) connected to the actuator arm to cause movement of the actuator arm, the VCM configured to receive a signal to move the actuator arm so that the transducer is moved relative to the disk;
• a processor coupled to receive servo data read from the magnetic media tracks using the transducer and to provide current command signals indicating actuator movement should occur;
• a VCM control circuit configured to receive the servo current command signals from the processor and to provide current to the VCM in response to control movement of the actuator;
• and
• a clock signal generation circuit connected to selectively provide one of a plurality of different clock signals having different clock rates to the processor, wherein a first one of the clock signals is provided having a first clock rate when a servo interrupt code is initially processed by the processor until a resulting servo current command signal is provided from the processor to the VCM control circuit, and wherein a second one of the clock signals is provided having a second clock rate less which is less than the first clock rate when additional code is processed to limit power consumption of the processor.

A disk drive system comprising:

• a rotatable disk containing magnetic media with data recordable in defined tracks;
• a transducer;
• an actuator arm that supports the transducer;
• a voice control motor (VCM) connected to the actuator arm to cause movement of the actuator arm, the VCM configured to receive a signal to move the actuator arm so that the transducer is moved relative to the disk;
• a processor coupled to receive servo data read from the magnetic media tracks using the transducer and to provide servo current command signals indicating actuator movement should occur;
• a VCM control circuit configured to receive the servo current command signals from the processor and to provide current to the VCM in response to control movement of the actuator;
• and
• a clock signal generation circuit connected to selectively provide one of a plurality of different clock signals having different clock rates to the processor, wherein a first one of the clock signals is provided having a first clock rate when a data request code is initially processed by the processor until a resulting track seeking servo current command signal is provided from the processor to the VCM control circuit, and wherein a second one of the clock signals is provided having a second clock rate less which is less than the first clock rate when additional code is processed by the processor.