Array substrate for a liquid crystal display device and method for fabricating thereof having vertical pattern

A method of fabricating an array substrate, comprising:

• forming a first metal layer on a substrate;
• patterning the first metal layer to form a first gate shorting bar, a vertical pattern, a plurality of odd gate lines, each having an associated odd gate pad and gate electrodes, and a plurality of even gate lines, each having an associated even gate pad and gate electrodes, wherein the vertical pattern electrically connects the odd gate pads and the even gate pads together;
• forming a gate insulation layer over the substrate and over the patterned first metal layer;
• forming an active layer and an ohmic contact layer over each gate electrode;
• forming a second metal layer over the gate insulation layer and over the ohmic contact layers;
• patterning the second metal layer to form a second shorting bar and a plurality of data lines, a plurality of source electrodes, and a plurality of drain electrodes, wherein each source electrode and each drain electrode is formed over an associated ohmic contact layer;
• forming a passivation layer over the patterned second metal layer;
• patterning the passivation layer to form drain contact holes to the drain electrodes, odd gate pad contact holes to the odd gate pads, even gate pad contact holes to the even gate pads, first connecting contact holes to the first gate shorting bar, second connecting contact holes to the second gate shorting bar, and etching holes to the vertical pattern;
• forming a transparent conductive layer over the patterned passivation layer;
• and
• patterning the transparent conductive layer to form pixel electrodes, first pad connectors that electrically connect the first gate shorting bar to associated odd gate pads via the first connecting contact holes and via the odd gate pad contact holes, and second pad connectors that electrically connect the second gate shorting bar to associated even gate pads via the second connecting contact holes and via the even gate pad contact holes;
• wherein patterning the transparent conductive layer etches the vertical pattern via the etching holes such that the odd gate pads are electrically isolated from the even gate pads.