Synchronizing video formats with dissimilar timing
AssigneeSun Microsystems, Inc.
InventorNathaniel David Naegle
Life of this patent
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Abstract
In order to synchronize two dissimilar video formats, two or more phase locked loop circuits (PLL's) may be used in tandem. A first PLL circuit may be connected to the first video format (Master) and generate an intermediate frequency. A second PLL circuit may use the intermediate frequency as the timebase for generating the pixel clock for the second video format (Slave). One or more Slaves may be connected to the generated pixel clock. The video synchronizing device may be a part of a graphics system, such as a graphics accelerator.
Claims34
A video synchronizing device, wherein the video synchronizing device is operable to synchronize a first video signal having a first video format and a second video signal having a second video format, both video signals having the same frame rate, the video synchronizing device comprising:
- a genlock signal input terminal operable to receive a genlock signal from the first video signal, and propagate a stripped genlock signal of a first frequency;
- a first phase-locked loop circuit operable to receive at least a part of the stripped genlock signal and produce an intermediate signal of an intermediate frequency;
- and
- a second phase-locked loop circuit operable to receive the intermediate signal and produce a final signal of a final frequency;
- wherein the first video signal is synchronized with video frame timing of the second video signal;
- and
- wherein one or more of the first-phase locked loop and the second phase locked loop are operable to adjust the phase of the intermediate signal with respect to the genlock signal.
A method to synchronize two video signals, wherein a first video signal has a first video format and a second video signal has a second video format, both video signals have the same frame rate, the method comprising:
- receiving a genlock signal from the first video signal;
- stripping the genlock signal in order to propagate a stripped genlock signal of a first frequency;
- a first phase-locked loop circuit receiving at least a part of the stripped genlock signal and producing an intermediate signal of an intermediate frequency;
- and
- a second phase-locked loop circuit receiving the intermediate signal and producing a final signal of a final frequency;
- wherein the first phase-locked loop and the second phase-locked loop are coupled together;
- wherein the first video signal is synchronized with video frame timing of the second video signal;
- wherein the final frequency of the final signal is substantially equal to:
- F
- Final
- =
- F
- 1
- ×
- M
- 1
- ×
- M
- 2
- N
- 2
- ;
- wherein F1 is the frequency of the at least a part of the stripped genlock signal;
- wherein M1 is the value of an internal frequency multiplier of the first phase-locked loop circuit;
- wherein M2 is the value of an internal frequency multiplier of the second phase-locked loop circuit;
- wherein N2 is the value of an internal frequency divider of the second phase-locked loop circuit, and
- wherein FFinal is the final frequency of the final signal.
A graphics system, comprising:
- one or more filtering units, wherein the one or more filtering units are operable to filter samples and thereby produce pixels, wherein each one of the one or more filtering units comprises one or more video synchronizing devices, wherein the one or more video synchronizing devices are operable to synchronize two video signals with different formats;
- wherein each one of one or more video synchronizing devices is operable to synchronize a first video signal having a first video format and a second video signal having a second video format, both video signals having the same frame rate, the video synchronizing device comprising:
- a genlock signal input terminal operable to receive a genlock signal from the first video signal, and propagate a stripped genlock signal of a first frequency;
- a first phase-locked loop circuit operable to receive at least a part of the stripped genlock signal and produce an intermediate signal of an intermediate frequency;
- and
- a second phase-locked loop circuit operable to receive the intermediate signal and produce a final signal of a final frequency;
- and
- wherein the first video signal is synchronized with video frame timing of the second video signal.
A video synchronizing device, wherein the video synchronizing device is operable to synchronize a first video signal having a first video format and a second video signal having a second video format, both video signals having the same frame rate, the video synchronizing device comprising:
- a genlock signal input terminal operable to receive a genlock signal from the first video signal, and propagate a stripped genlock signal of a first frequency;
- a first phase-locked loop circuit operable to receive at least a part of the stripped genlock signal and produce an intermediate signal of an intermediate frequency;
- and
- two or more second phase-locked loop circuits operable to receive the operated intermediate signal and produce a final signal of a final frequency, wherein the two or more second phase-locked loop circuits are operable to synchronize the first video signal with the second video signal using video synchronization signals;
- wherein the final frequency of the final signal is substantially equal to:
- F
- Final
- =
- F
- 1
- ×
- M
- 1
- ×
- M
- 2
- N
- 2
- ;
- wherein F1 is the frequency of the at least a part of the stripped genlock signal:
- wherein M1 is the value of an internal frequency multiplier of the first phase-locked loop circuit:
- wherein M2 is the value of an internal frequency multiplier of the second phase-locked loop circuit:
- wherein N2 is the value of an internal frequency divider of the second phase-locked loop circuit, and
- wherein FFinal is the final frequency of the final signal.
A video synchronizing device, wherein the video synchronizing device is operable to synchronize a first video signal having a first video format and a second video signal having a second video format, both video signals having a same frame rate, the video synchronizing device comprising:
- a genlock signal input terminal operable to receive a genlock signal from the first video signal, and propagate a stripped genlock signal of a first frequency;
- a first phase-locked loop circuit operable to receive at least a part of the stripped genlock signal and produce an intermediate signal of an intermediate frequency;
- and
- a second phase-locked loop circuit operable to receive the intermediate signal and produce a final signal of a final frequency, wherein the second phase-locked loop circuit is operable to synchronize the first video signal with the second video signal;
- wherein the intermediate signal has a selected phase difference with the genlock signal.
A video synchronizing device, wherein the video synchronizing device is operable to synchronize a first video signal having a first video format and a second video signal having a second video format, both video signals having the same frame rate, the video synchronizing device comprising:
- a genlock signal input terminal operable to receive a genlock signal from the first video signal, and propagate a stripped genlock signal of a first frequency;
- a first phase-locked loop circuit operable to receive at least a part of the stripped genlock signal and produce an intermediate signal of an intermediate frequency;
- and
- a second phase-locked loop circuit operable to receive the intermediate signal and produce a final signal of a final frequency;
- wherein the final frequency of the final signal is substantially equal to:
- F
- Final
- =
- F
- 1
- ×
- M
- 1
- ×
- M
- 2
- N
- 2
- ;
- wherein F1 is the frequency of the at least a part of the stripped genlock signal;
- wherein M1 is the value of an internal frequency multiplier of the first phase-locked loop circuit;
- wherein M2 is the value of an internal frequency multiplier of the second phase-locked loop circuit;
- wherein N2 is the value of an internal frequency divider of the second phase-locked loop circuit, and
- wherein FFinal is the final frequency of the final signal.
Dependencies are inferred from the claim text.