System and method for scheduling access to an analog-to-digital converter and a microprocessor
AssigneeSigmatel, Inc.
InventorDavid Cureton Baker
Life of this patent
Estimating the term…
Abstract
A method of scheduling use of an analog-to-digital converter is disclosed and includes writing to a schedule register that has a plurality of schedule bits. Each of the plurality of schedule bits corresponds to a channel of an analog-to-digital converter. Further, the method includes copying the plurality of bits from the schedule register to a request register that has a plurality of request bits. The method also includes monitoring the plurality of request bits and determining whether at least one of the plurality of request bits is set. Additionally, the method includes blocking further copying to the request register after determining that at least one of the plurality of request bits is set.
Claims30
A method of scheduling use of an analog-to-digital converter, the method comprising:
- writing to a schedule register having a plurality of schedule bits, wherein each of the plurality of schedule bits corresponds to a channel of an analog-to-digital converter;
- copying the plurality of bits from the schedule register to a request register having a plurality of request bits;
- monitoring the plurality of request bits;
- determining whether at least one of the plurality of request bits is set;
- and
- blocking further copying to the request register after determining that at least one of the plurality of request bits is set.
An analog-to-digital converter system, comprising:
- a controller;
- a programmable control register coupled to the controller;
- a plurality of channels coupled to the controller, each channel having an associated schedule bit within the programmable control register, an associated request bit within the programmable control register, and an associated interrupt request bit within the programmable control register;
- and
- a scheduler coupled to the controller and to the programmable control register, the scheduler comprising logic to monitor a plurality of request bits to detect when any of the schedule request bits are set.
A semiconductor device, comprising:
- a microprocessor;
- an analog-to-digital converter coupled to the microprocessor, the analog-to-digital converter comprising:
- a controller;
- a schedule register, a request register, and an interrupt request register coupled to the controller;
- a plurality of channels coupled to the controller, each channel having an associated schedule bit within the schedule register, an associated request bit within the request register, and an associated interrupt request bit within the interrupt request register;
- and
- a scheduler coupled to the controller and the registers, the scheduler comprising:
- logic to copy a plurality of schedule bits to a plurality of request bits;
- logic to monitor the plurality of request bits, logic to determine whether at least one of the plurality of request bits is set;
- and
- logic to block further copying of the schedule bits when at least one of the plurality of request bits is set.
Dependencies are inferred from the claim text.