Monolithic CMOS differential LNA with enhanced linearity

A low noise amplifying (LNA) circuitry, having a differential input pair consisting of a positive input terminal and a negative input terminal, and a differential output pair consisting of a positive output terminal and a negative output terminal, comprising:

• a first cascode amplifying module;
• a second cascade amplifying module;
• a current source, controlled by a bias voltage level, for supplying current to the LNA circuitry;
• a first resonant tank, coupled to the negative output terminal as output load;
• and
• a second resonant tank, coupled to the positive output terminal as output load;
• wherein,
• the first cascode amplifying module comprises:
• a first transistor, having a channel width/length ratio r1,
• a second transistor, having a channel width/length ratio r2,
• a third transistor, having a channel width/length ratio r3, and
• a fourth transistor, having a channel width/length r4;
• and
• the second cascade amplifying module comprises:
• a first auxiliary transistor, having a channel width/length ratio r1′,
• a second auxiliary transistor, having a channel width/length ratio r2′,
• a third auxiliary transistor, having a channel width/length ratio r3′, and
• a fourth auxiliary transistor, having a channel width/length ratio r4′,
• wherein r1, r2, r3, r4, r1′, r2′, r3′, and r4′ are selected such that
• r4
• =
• r3
• ,
• r4
• ′
• =
• r3
• ′
• ,
• r
• 1
• r
• 3
• =
• r
• 1
• ′
• r
• 3
• ′
• ,
• B
• ≈
• r
• 1
• r
• 2
• ,
• A
• ≈
• r
• 1
• r
• 1
• ′
• ,
• and
• ⁢
• ⁢
• A
• =
• B
• 3
• ,
• and
• the ratios of the first, second, third and fourth transistors are later than those of the first, second, third and fourth auxiliary transistors.