High-speed low-power dynamic current biased operational amplifier
AssigneesSony Corporation, Sony Electronics Inc.
InventorIain Christopher Butler
Life of this patent
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Abstract
A high-speed low-power dynamic current biased operational amplifier (Op-amp) for use in switched capacitor circuits. The system and method reduces current in the reset process of the switched capacitor circuit's operation, while maintaining the drive current required for fast settling in the amplification process. The system and method significantly lowers the power consumption of the switched capacitor circuit, while overcoming the main issues related to dynamic current biasing in an Op-amp, common-mode feedback interaction, using architecture other than the standard differential input stage of a normal Op-amp.
Claims45
An operational amplifier for use in a switched capacitor circuit, the operational amplifier comprising:
- a grounded source operational amplifier circuit;
- a dynamic current switching circuit coupled to the grounded source operational amplifier circuit, wherein the dynamic current switching circuit is configured to reduce power dissipation in the grounded source operational amplifier circuit;
- and
- an upper gain enhancement circuit including a first PMOS cascode, a second PMOS cascode, and an AUXP operational amplifier, wherein the upper gain enhancement circuit maintains an upper gain bias voltage across a first PMOS current source and across a second PMOS current source.
An operational amplifier for use in a switched capacitor circuit, the operational amplifier comprising:
- a grounded source operational amplifier circuit, wherein the grounded source operational amplifier circuit includes:
- a main amplifier core circuit;
- and
- a biasing circuit;
- a dynamic current switching circuit coupled to the grounded source operational amplifier circuit, wherein the dynamic current switching circuit is configured to reduce power dissipation in the grounded source operational amplifier circuit;
- and
- a first main leg and a second main leg in a branch of the main amplifier core circuit, wherein the first main leg and the second main leg are configured such that an input pair bias current and an output pair bias current flow in the branch.
An operational amplifier for use in a switched capacitor circuit, the operational amplifier comprising:
- a main amplifier core circuit including:
- a first main leg and a second main leg in a branch of the main amplifier core circuit, wherein the first main leg and the second main leg are configured such that an input pair bias current and an output pair bias current flow in the branch,
- an upper gain enhancement circuit including a first PMOS cascode, a second PMOS cascode, and an AUXP operational amplifier, wherein the upper gain enhancement circuit maintains an upper gain bias voltage across a first PMOS current sources and a second PMOS current source, and
- a lower gain enhancement circuit including a first NMOS cascode, a second NMOS cascade, and an AUXN operational amplifier, wherein the lower gain enhancement circuit maintains a lower gain bias voltage across a main input pair;
- a biasing circuit;
- and
- a dynamic current switching circuit coupled to the main amplifier core circuit,
- wherein the dynamic current switching circuit is configured to reduce power dissipation in the main amplifier core circuit.
An operational amplifier for use in a switched capacitor circuit, the operational amplifier comprising:
- a main amplifier core circuit including a first main leg and a second main leg in a branch of the main amplifier core circuit, wherein the main amplifier core circuit includes an upper gain enhancement circuit including a first PMOS cascode, a second PMOS cascode, and an AUXP operational amplifier, and wherein the upper gain enhancement circuit maintains an upper gain bias voltage across a first PMOS current source and a second PMOS current source;
- a biasing circuit;
- and
- a dynamic current switching circuit coupled to the main amplifier core circuit,
- wherein the dynamic current switching circuit is configured to reduce power dissipation in the operational amplifier circuit.
A method of processing a signal in an operational amplifier, the method comprising:
- amplifying the signal with a main amplifier core circuit, the main amplifier core circuit including a first main leg and a second main leg in a branch of the main amplifier core circuit, wherein the main amplifier core circuit includes an upper gain enhancement circuit including a first PMOS cascode, a second PMOS cascode, and an AUXP operational amplifier, and wherein the upper gain enhancement circuit maintains an upper gain bias voltage across a first PMOS current source and a second PMOS current source;
- biasing the signal with a biasing circuit;
- and
- reducing power dissipation with a dynamic current switching circuit coupled to the main amplifier core circuit.
Dependencies are inferred from the claim text.