Apparatus and method for reducing propagation delay

A timer circuit for reducing propagation delay for a relatively small supply voltage, comprising:

• a current mirror having at least an input and an output, wherein the current mirror is arranged to receive a reference current at an input of the current mirror, and to provide a current at the output of the current mirror based on the reference current;
• a capacitor circuit that is operable to provide a first voltage in response to the current;
• a voltage offset circuit that is coupled between the current source circuit and the capacitor circuit, wherein the voltage offset circuit is operable to provide a second voltage in response to the first voltage and the current such that the second voltage is positively offset relative to the first voltage;
• and
• an inverter circuit that includes a p-type transistor and an n-type transistor, wherein a drain of the p-type transistor is coupled to a drain of the n-type transistor, a gate of the p-type transistor is operable to receive the first voltage, and a gate of the n-type transistor is operable to receive the second voltage.

A timer circuit for reducing propagation delay for a relatively small supply voltage, comprising:

• a current source circuit having at least an output that is coupled to a first node, wherein the current source circuit is operable to provide a current;
• a capacitor circuit that is coupled between a second node and a third node, wherein the second node is coupled to ground, and wherein the capacitor circuit is operable to provide a first voltage at the third node;
• a voltage offset circuit that is coupled between the first node and the third node, wherein the voltage offset circuit is operable to provide a second voltage in response to the first voltage and the current such that the second voltage is positively offset relative to the first voltage;
• and
• an inverter circuit that includes:
• a p-type transistor having at least a gate, a drain, and a source, wherein the gate of the p-type transistor is coupled to the third node, the drain of the p-type transistor is coupled to a fourth node, and the source of the p-type transistor is coupled to a fifth node;
• the fifth node is a power supply node;
• and wherein, regardless of the logic level at the gate of the p-type transistor, the capacitor circuit is electrically coupled between the gate of the p-type transistor and the second node;
• and
• an n-type transistor having at least a gate, a drain, and a source, wherein the gate of the n-type transistor is coupled to the first node, the drain of the n-type transistor is coupled to the fourth node, and the source of the n-type transistor is coupled to the second node.