Clock multiplexing system
AssigneeXilinx, Inc.
InventorsVasisht Mantra Vadi, Steven P. Young
Life of this patent
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Abstract
A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second differential multiplexers coupled to the first differential multiplexers and configured to select second outputs from the first outputs; loop back signal lines configured to feed back the second outputs to at least part of the input clock signals of the first differential multiplexers; and differential signal lines of the differential clock tree coupled to the second outputs.
Claims15
A clock control circuit in an integrated circuit for providing a clock signal to a clock tree, comprising:
- a first plurality of multiplexers configured to select a first plurality of outputs from input clock signals;
- a second plurality of multiplexers coupled to the first plurality of multiplexers and configured to select a second plurality of outputs from the first plurality of outputs;
- a plurality of loop back signal lines configured to feed back the second plurality of outputs to at least part of the input clock signals of the first plurality of multiplexers;
- a plurality of signal lines of the clock tree coupled to the second plurality of outputs;
- and
- a plurality of current driver circuits coupled between the second plurality of outputs and the plurality of signal lines of the clock tree, wherein the signal lines of the clock tree are differential signal lines, and wherein the plurality of current driver circuits are configured to convert rail-to-rail differential signals to small signal differential signals.
A clock control circuit in an integrated circuit comprising:
- a plurality of converters configured to input small signal differential clock signals and to output two phase full complementary metal oxide semiconductor (CMOS) differential clock signals;
- a switch coupled to the plurality of converters for receiving the two phase full complementary metal oxide semiconductor (CMOS) differential clock signals;
- and
- a driver circuit coupled to an output of the switch and sending a small signal differential global clock signal based on the output to a small signal differential clock tree located on the integrated circuit.
A programmable logic device having a clock control circuit for providing a differential clock signal to a differential clock tree of the programmable logic device, the clock control circuit comprising:
- a first plurality of configurable differential multiplexers configured to select a first plurality of output signals from input clock signals;
- a second plurality of configurable differential multiplexers coupled to the first plurality of configurable differential multiplexers and configured to select a second plurality of output signals from the first plurality of output signals;
- a plurality of loop back signal lines configured to feed back the second plurality of output signals to at least part of the input clock signals of the first plurality of differential multiplexers;
- and
- a plurality of current driver circuits coupled between a plurality of differential signal lines of the differential clock tree and the second plurality of output signals, wherein the plurality of current driver circuits are configured to convert rail-to-rail differential signals to small signal differential signals.
A muxing system comprising:
- a first set of multiplexers directly connected to a second set of multiplexers, wherein the second set of multiplexers comprises a plurality of 2:1 differential multiplexers;
- a first multiplexer of the second set of multiplexers selecting from at least first and second input signals and producing a first output signal;
- a first multiplexer of the first set of multiplexers receiving the first output signal and producing a second output signal;
- a second multiplexer of the second set of multiplexers selecting from the second output signal and at least a third input signal and producing a third output signal;
- and
- wherein a multiplexer of the plurality of 2:1 differential multiplexers comprises:
- control logic having:
- a plurality of control terminals receiving a corresponding plurality of control signals;
- and
- at least one state terminal providing a state signal responsive to a state of a plurality of states;
- wherein the control logic defines the plurality of states, including at least first and second states, in response to the control signals;
- and
- a clock multiplexer having:
- at least one select terminal connected to the state terminal;
- first differential input terminals receiving a first differential clock signal;
- second differential input terminals receiving a second differential clock signal;
- and
- differential output terminals transmitting the first differential clock signal in the first state or the second differential clock signal in the second state, depending, at least in part, upon the state signal.
Dependencies are inferred from the claim text.