Clock control circuit and method
AssigneeNEC Electronics Corporation
InventorTakanori Saeki
Life of this patent
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Abstract
A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.
Claims11
A clock controlling circuit comprising:
- a frequency dividing circuit for frequency dividing input clocks for outputting frequency divided multi-phase clocks of plural different phases;
- a plurality of clock propagation paths for receiving at one end with a plurality of frequency divided clocks output from said frequency dividing circuit;
- a plurality of timing averaging circuits for receiving two clocks from a first position on a forward route and from a second position on a return route corresponding to said first position, for each of said plural clock propagation paths, each to output an output signal of delay time corresponding to a time resulting from division of a timing difference of said two clocks into two equal portions, respectively;
- and
- a synthesis circuit for synthesizing plural outputs of said plural timing averaging circuits.
A clock controlling circuit comprising:
- means for frequency dividing input clocks for outputting frequency divided multi-phase clocks of plural different phases;
- a plurality of means for receiving at one end with a plurality of frequency divided clocks output from said means for frequency dividing input clocks;
- means for receiving two clocks from a first position on a forward route and from a second position on a return route corresponding to said first position, for each of said means for receiving, outputting an output signal of delay time corresponding to a time resulting from division of a timing difference of said two clocks into two equal portions, respectively;
- and
- means for synthesizing plural outputs of said means for receiving two clocks.
A method for controlling a clock comprising:
- frequency dividing input clocks for outputting frequency divided multi-phase clocks of plural different phases;
- receiving said frequency divided multi-phase clocks of plural different phases at one end of a plurality of clock propagation paths;
- receiving two clocks from a first position on a forward route and from a second position on a return route corresponding the first position;
- outputting an output signal of a delay time corresponding to a time resulting from a division of a timing difference of said two clocks into two equal portions, respectively;
- and
- synthesizing plural outputs of said plural timing averaging circuits.
Dependencies are inferred from the claim text.