Semiconductor integrated circuit and manufacturing method
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorHiroyuki Tahara
Life of this patent
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Abstract
In order to provide a semiconductor integrated circuit equipped with a clock distribution circuit that enables clock skew to be reduced without requiring great effort and without being affected by temperature variations or voltage variations, and a manufacturing method thereof, in a clock distribution circuit 1 installed in a semiconductor integrated circuit, part of the distribution path of a clock signal that passes from a first selector 11 of a first circuit block 10 that has many buffer stages via a first buffer stage 10A is used, and a distribution path of a clock signal to a second buffer stage 20A of a second circuit block 20 that has few buffer stages is constructed.
Claims4
A semiconductor integrated circuit equipped with a clock distribution circuit comprising:
- a first circuit block in which a plurality of first buffer stages are arranged according to a buffer tree structure and a clock signal output from a first selector is distributed to said plurality of first buffer stages;
- and
- a second circuit block in which second buffer stages of fewer stages compared with said first circuit block are arranged according to a buffer tree structure and the clock signal output from said first selector is distributed to a second buffer stage via said first buffer stage and a second selector.
A manufacturing method of a semiconductor integrated circuit equipped with a clock distribution circuit comprising:
- a step of placing a first circuit block in which a plurality of first buffer stages are arranged according to a buffer tree structure and a clock signal output from a first selector is distributed to said plurality of first buffer stages;
- a step of placing a second circuit block in which second buffer stages comprising fewer stages compared with said first circuit block are arranged according to a buffer tree structure and a clock signal output from a second selector is distributed to second buffer stages;
- and
- a step of placing a connecting wire that supplies the clock signal from said first selector to said second selector via said first buffer stages.
Dependencies are inferred from the claim text.