US 7,071,749 B2 · Error correcting latch

Abstract

An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Claims20

Dependent claims

An error-correcting latch comprising:

first, second, and third error-correcting latch stages each including a clock input;
and
first, second, and third clock signal buses respectively coupled to the clock input of the first, second, and third error-correcting latch stages through a first, second, and third driver circuit, and
wherein each latch stage further comprises a two-of-three voting circuit placed in a feedback loop of the latch stage.

1 more element

Dependencies are inferred from the claim text.

Error correcting latch

Life of this patent

Error correcting latch

Life of this patent

Abstract

Claims20