Charge pump clock for non-volatile memories
AssigneeAtmel Corporation
InventorMathew T. Wich
Life of this patent
Estimating the term…
Abstract
A charge pump clock for a memory device wherein pump clock signals are generated at an adaptive rate. The circuit of the present invention generates clock edges at a minimum of TD seconds apart so long as address transitions do not exceed a pre-determined limit. However, if address changes are occurring more frequently than this limit, i.e., 1/(2*TD), then clock edges will be generated at a rate that is proportional to the rate of address changes, where TD is approximately half of the address period. Two logic rules are implemented in hardware or equivalent software to make the clock signal adjustments.
Claims10
In a charge pump clock generating a pump clock signal, a logic circuit executing an algorithm with the following steps:
- if said pump clock signal is in a first pump clock state for at least a predetermined period of time, switching said pump clock signal from said first pump clock state to a second pump clock state;
- and
- if said pump clock signal is in said second pump clock state for at least said predetermined period of time, switching said pump clock signal from said second pump clock state to said first pump clock state;
- and
- if at a rising edge of a positive logic pulse a read clock signal changes its state from a first read clock state to a second read clock state, or from said second read clock state to said first read clock state, causing said pump clock signal to change said pump clock signal state at a falling edge of said positive logic pulse unless:
- {(i) said pump clock signal changed said pump clock signal state at said rising edge of said positive logic pulse;
- and (ii) said read clock state change at said rising edge of said positive logic pulse is the first one since said most recent pump clock signal state change}.
A charge pump clock for generating a pump clock signal comprising:
- a first and second logic rule circuit means wherein said first logic rule circuit means is arranged for executing the following steps:
- if said pump clock signal is in a first pump clock state for at least a predetermined period of time, switching said pump clock signal from said first pump clock state to a second pump clock state;
- and
- if said pump clock signal is in said second pump clock state for at least said predetermined period of time, switching said pump clock signal from said second pump clock state to said first pump clock state;
- and
- wherein said second logic rule circuit means is arranged for executing the following steps:
- if at a rising edge of a positive logic pulse a read clock signal changes its state from a first read clock state to a second read clock state, or from said second read clock state to said first read clock state, causing said pump clock signal to change said pump clock signal state at a falling edge of said positive logic pulse unless:
- {(i) said pump clock signal changed said pump clock signal state at said rising edge of said positive logic pulse;
- and (ii) said read clock state change at said rising edge of said positive logic pulse is the first one since said most recent pump clock signal state change}.
Dependencies are inferred from the claim text.