Variable delay circuit

A variable delay circuit for delaying and outputting a reference clock signal or a data signal, comprising:

• plural stages of first variable delay elements coupled in series for sequentially delaying said reference clock signal or data signal;
• a second variable delay element coupled in parallel to said plural stages of first variable delay elements for delaying said reference clock signal;
• a phase comparator for comparing a phase of said reference clock signal delayed by said plural stages of first variable delay elements with a phase of said reference clock signal delayed by said second variable delay element, said phase comparator inputting output signals of both said first variable delay elements and said second variable delay element;
• and
• a delay amount control unit connecting to an output of said phase comparator for controlling a delay amount of each of said plural stages of first variable delay elements based on a comparison result of said phase comparator in order that said phase of said reference clock signal delayed by said plural stages of first variable delay elements is substantially the same as said phase of said reference clock signal delayed by said second variable delay element after predetermined cycles;
• wherein said phase comparator comprises:
• a dynamic D flip-flop circuit for latching and outputting said reference clock signal delayed by said plural stages of first variable delay elements with parasitic capacitance thereof based on said reference clock signal delayed by said second variable delay element;
• and
• a D flip-flop circuit for latching and outputting an output signal outputted by said dynamic D flip-flop circuit based on said reference clock signal delayed by said second variable delay element.

A variable delay circuit for delaying and outputting a reference clock signal or a data signal, comprising:

• plural stages of first variable delay elements coupled in series for sequentially delaying said reference clock signal or data signal;
• a second variable delay element coupled in parallel to said plural stages of first variable delay elements for delaying said reference clock signal;
• a phase comparator for comparing a phase of said reference clock signal delayed by said plural stages of first variable delay elements with a phase of said reference clock signal delayed by said second variable delay element, said phase comparator inputting output signals of both said first variable delay elements and said second variable delay element;
• and
• a delay amount control unit connecting to an output of said phase comparator for controlling a delay amount of each of said plural stages of first variable delay elements based on a comparison result of said phase comparator in order that said phase of said reference clock signal delayed by said plural stages of first variable delay elements is substantially the same as said phase of said reference clock signal delayed by said second variable delay element after predetermined cycles;
• wherein said phase comparator outputs a flag signal indicating whether said phase of said clock signal delayed by said plural stages of first variable delay elements is early or late relatively to said phase of said clock signal delayed by said second variable delay element, and said delay amount control unit comprises:
• a counter for increasing a count value if said flag signal indicates that said phase of said clock signal delayed by said plural stages of first variable delay elements is early, whereas decreasing said count value if said flag signal indicates that said phase is late;
• and
• a DAC for supplying a bias signal to control said delay amount for at least one of said plural stages of first variable delay elements based on said count value of said counter.