Interrupt-based phase-locked frequency multiplier

A method for generating an output signal at a frequency that is N times a frequency of an input signal and phase-locked to said input signal, comprising the steps of:

• providing processing means having (i) a digital timer adjustable to operate at a known timer clock rate to generate an overflow signal each time said digital timer counts to a count value CV at said timer clock rate, and (ii) a plurality of interrupts to include a first interrupt having a first time window associated therewith during which processing occurs and a second interrupt having a second time window associated therewith during which processing occurs, said first time window definable by a first number of counts C1 of said digital timer and said second time window definable by a second number of counts C2 of said digital timer, wherein said count value CV is based on a desired frequency multiplier N, said timer clock rate, and time required for one cycle of said input signal, and wherein said overflow signal is generated N times for said one cycle and wherein said count value CV is greater than (C1+C2) such that said first time window and said second time window begin and elapse in a non-overlapping fashion during the time it takes for said digital timer to count to said count value CV;
• initializing said digital tinier such that said first time window begins at a timer count TC of said digital timer defined as TC=IC−0.5(C1) where an interim count IC defines a number of courts counted by said digital timer before said digital timer counts to said count value CV, wherein said first time window is approximately centered at said interim count IC and wherein said first time window and said second time window do not overlap;
• triggering said first interrupt upon completion of said one cycle of said input signal, at which point said first time window begins;
• triggering said second interrupt each time said overflow signal is generated, at which point said second time window begins;
• and
• modifying, during the occurrence of said second time window, said count value CV to maintain said first time window approximately centered at said interim count IC.

A frequency multiplier comprising processing means having (i) a digital timer adjustable to operate at a known timer clock rate to generate an overflow signal each time said digital timer counts to a count value CV at said timer clock rate, and (ii) a plurality of interrupts to include a first interrupt having a first dine window associated therewith during which processing occurs and a second interrupt having a second time window associated therewith during which processing occurs, said first time window definable by a first number of counts C1 of said digital timer and said second time window definable by a second number of counts C2 of said digital timer, wherein said count value CV is based on a desired frequency multiplier N, said timer clock rate, and time required for one cycle of an input signal, and wherein said overflow signal is generated N times for said one cycle and wherein said count value CV is greater than (C1+C2) such that said first time window and said second time window begin and elapse in a non-overlapping fashion during the time it takes for said digital timer to count to said count value CV,

• said digital timer being initialized such that said first time window begins at a timer count TC of said digital timer defined as TC=IC−0.5(C1) where an interim count IC defines a number of counts counted by said digital timer before said digital timer counts to said count value CV, wherein said first time window is approximately centered at said interim count IC and wherein said first time window and said second time window do not overlap,
• said first interrupt adapted to receive said input signal for triggering upon completion of said one cycle of said input signal, at which point said first time window begins,
• said second interrupt coupled to said digital timer for triggering each time said overflow signal is generated, at which point said second time window begins, and
• said processing means modifying, during the occurrence of said second time window, said count value CV to maintain said first time window approximately centered at said interim count IC.