Termination sense-and-match differential driver

A differential driver circuit comprising:

• an output driver circuit including:
• differential amplifier circuitry that is configured to provide a differential output signal in response to a differential input signal;
• a first variable resistance circuit that is configured to vary a resistance that is associated with the first variable resistance circuit in response to a first control signal;
• and
• a second variable resistance circuit that is configured to vary a resistance that is associated with the second variable resistance circuit in response to a second control signal;
• and
• a feedback circuit that is configured to provide the first control signal and the second control signal, wherein a source resistance of the output driver circuit appears to a load as substantially similar to a termination resistance of the load,
• wherein the output driver circuit is further configured to provide a monitor signal,
• the feedback circuit includes:
• a third variable resistance circuit that is configured to vary a resistance that is associated with the third variable resistance circuit in response to the first control signal,
• wherein the third variable resistance circuit is a replica of the first variable resistance circuit;
• a fourth variable resistance circuit that is configured to vary a resistance that is associated with the fourth variable resistance circuit in response to the second control signal, wherein
• the fourth variable resistance circuit is a replica of the second variable resistance circuit;
• a transistor that is coupled between the third variable resistance circuit and the fourth variable resistance circuit;
• a first operational amplifier that is configured to provide the first control signal;
• a second operational amplifier that is configured to provide the second control signal;
• and
• a third operational amplifier circuit that is coupled to the first variable resistance circuit, the third variable resistance circuit, and the transistor wherein
• the third operational amplifier circuit is configured to modulate the transistor in response to the monitor signal such that the first current source circuit and the second current source circuit each provide approximately constant current,
• wherein the output driver circuit further includes:
• a first current source circuit that is coupled to the first variable resistance circuit and the feedback circuit;
• and
• a first current sink circuit that is coupled to the second variable resistance circuit and the feedback circuit,
• the feedback circuit further includes:
• a second current source circuit that is a replica of the first current source circuit;
• a second current sink circuit that is a replica of the first current sink circuit;
• a fourth operational amplifier circuit that is configured to bias the first and second current source circuits in response to a first upper reference signal and a first feedback signal;
• and
• a fifth operational amplifier circuit that is configured to bias the first and second current sink circuits in response to a first lower reference signal and a second feedback signal,
• the transistor is coupled between a first feedback node and a second feedback node,
• the first operational amplifier circuit is configured to provide the first control signal in response to a third feedback signal that is received at the first feedback node and a second upper reference signal, and
• wherein the second operational amplifier circuit is configured to provide the second control signal in response to a fourth feedback signal that is received at the second feedback node and a second lower reference signal.

A differential driver circuit, comprising:

• an output driver circuit, including:
• differential amplifier circuitry;
• a first variable resistance circuit that is coupled to the differential amplifier circuitry;
• and
• a second variable resistance circuit that is coupled to the differential amplifier circuitry;
• and
• a feedback circuit that is configured to control a resistance that is associated with the first variable resistance circuit and a resistance that is associated with the second variable resistance circuit such that a source resistance of the output driver circuit tracks the termination resistance,
• wherein the output driver circuit further includes:
• a current source transistor that is arranged to provide a current responsive to a bias signal, wherein the current source transistor operates in a saturation region of operation or an active region of operation, the first variable resistance circuit is coupled between the current source circuit and the differential amplifier circuitry, and wherein the first variable resistance circuit is arranged to receive the current.

A differential driver circuit, comprising:

• an output driver circuit, including:
• differential amplifier circuit;
• a first variable resistance circuit that is coupled to the differential amplifier circuitry;
• and
• a second variable resistance circuit that is coupled to the differential amplifier circuitry;
• and
• a feedback circuit that is configured to control a resistance that is associated with the first variable resistance circuit and a resistance that is associated with the second variable resistance circuit such that a source resistance of the output driver circuit tacks the termination resistance, wherein
• the feedback circuit includes:
• a third variable resistance circuit;
• a fourth variable resistance circuit;
• a transistor that is coupled between the third variable resistance circuit and the fourth variable resistance circuit;
• a first op amp circuit that is coupled between the transistor and the third variable resistance circuit;
• and
• a second op amp circuit that is coupled between the transistor and the fourth variable resistance circuit.