Glitchless clock selection circuit using phase detection switching

A clock selection circuit for switching an output clock signal among a plurality of input clock signals in response to a clock select signal, comprising:

• an output multiplexer having inputs to receive the input clock signals, an output to provide the output clock signal, and a control terminal to receive a synchronized clock select signal;
• means for selectively updating the synchronized clock select signal with state changes in the clock select signal in response to a synchronization signal;
• and
• means for selectively asserting the synchronization signal if corresponding edges of a previously selected input clock signal and a newly selected input clock signal are synchronous.

A method for switching an output clock signal between first and second input clock signals in response to a clock select signal without halting the output clock signal, comprising:

• providing the first and second clock signals to corresponding inputs of an output multiplexer;
• receiving the clock select signal;
• determining whether corresponding edges of the first and second input clock signals are synchronous;
• selectively asserting a synchronization signal in response to the determining;
• and
• selectively propagating state changes in the clock select signal to a control terminal of the output multiplexer in response to the asserting.