Systems and methods for controlling timing in a circuit

A silicon-on-insulator (SOI) sense amplifier comprising:

• an operational portion of the sense amplifier;
• and
• an enabling portion of the sense amplifier coupled to the operational portion of the sense amplifier, wherein the enabling portion of the sense amplifier includes a plurality of serially configured transistors coupled between the operational portion and ground;
• wherein the enabling portion is coupled to the operational portion and configured to enable or disable the operational portion based upon overlap of a first timing signal that is affected by history effects and a second timing signal that is unaffected by the history effects;
• wherein the enabling portion of the sense amplifier further comprises a timing generation circuit which is configured to generate the first timing signal that is affected by the history effects by selectively routing pulses of a clock signal through either circuitry defining a short-delay path or circuitry defining a long-delay path, depending upon whether a select signal is asserted.

A silicon-on-insulator (SOI) sense amplifier comprising:

• an operational portion of the sense amplifier;
• and
• an enabling portion of the sense amplifier coupled to the operational portion;
• wherein the enabling portion is configured to enable or disable the operational portion based upon overlap of a first timing signal that is affected by history effects and a second timing signal that is unaffected by the history effects;
• wherein the enabling portion of the sense amplifier includes a timing generation circuit which is configured to generate the first timing signal that is affected by the history effects, wherein the timing generation circuit is configured to selectively delay pulses of a clock signal by either a short delay, or a long delay.

An enabling circuit configured to be coupled to an operational circuit to selectively enable the operational circuit, wherein the enabling circuit comprises:

• a plurality of serially configured transistors coupled between the operational circuit and ground;
• wherein at least one of the serially configured transistors is coupled to receive, and configured to be switched on and off by, a first timing signal that is unaffected by history effects;
• wherein at least one of the serially configured transistors is coupled to receive, and configured to be switched on and off by, a second timing signal that is affected by history effects;
• and
• wherein the operational circuit is enabled or disabled by overlap of the first timing signal and the second timing signal.

An enabling circuit configured to be coupled to an operational circuit to selectively enable the operational circuit, wherein the enabling circuit comprises:

• a plurality of serially configured transistors coupled between the operational circuit and ground,
• wherein at least one of the serially configured transistors is coupled to receive, and configured to be switched on and off by, a first timing signal that is unaffected by history effects, and
• wherein at least one of the serially configured transistors is coupled to receive, and configured to be switched on and off by, a second timing signal that is affected by the history effects, and
• wherein the operational circuit is enabled or disabled by overlap of the first timing signal and the second timing signal;
• a timing generation circuit which is configured to generate the second timing signal by selectively routing pulses of a clock signal through either circuitry defining a short-delay path or circuitry defining a long-delay path, depending upon whether a select signal is asserted.

A method for enabling a sense amplifier comprising:

• providing a sense amplifier, wherein the sense amplifier includes two or more serially configured transistors that selectively couple the sense amplifier to ground;
• providing a first timing signal that is affected by history effects to a corresponding one of the serially configured transistors;
• providing a second timing signal that is unaffected by the history effects to a corresponding one of the serially configured transistors;
• and
• controlling overlap of the first timing signal that is affected by the history effects with the second timing signal that is unaffected by the history effects to enable or disable the sense amplifier.

A method for enabling a sense amplifier comprising:

• providing a sense amplifier, wherein the sense amplifier includes two or more serially configured transistors that selectively couple the sense amplifier to ground;
• providing a first timing signal that is affected by history effects to a corresponding one of the serially configured transistors;
• providing a second timing signal that is unaffected by the history effects to a corresponding one of the serially configured transistors, wherein the first timing signal that is affected by the history effects and is received by the serially configured transistor is a signal corresponding to selection of the sense amplifier from a plurality of sense amplifiers;
• and
• controlling overlap of the second timing signal that is unaffected by history effects with the first timing signal that is affected by the history effects to enable or disable the sense amplifier, wherein overlap of the first timing signal and the second timing signal is controlled by selectively delaying pulses of a clock signal by either a short delay or a long delay to produce the first timing signal that is affected by history effects.