Scalable complex programmable logic device with segmented interconnect resources
AssigneeXilinx, Inc.
InventorsTetse Jang, Shi-dong Zhou
Life of this patent
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Abstract
A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and columns of function blocks and input/output (I/O) blocks programmably interconnected by a de-centralized interconnect structure. The interconnect structure includes numbers of interconnect lines segmented into shorter lengths. Programmable multiplexer circuits couple the segmented interconnect lines to the function blocks and I/O blocks. Programmable switch matrices couple the segmented interconnect lines together into longer interconnect lines of the desired length.
Claims21
A programmable logic device (PLD), comprising:
- a plurality of complex programmable logic device (CPLD) function blocks disposed to implement a two-dimensional array of the CPLD function blocks, each of the CPLD function blocks including a programmable logic array (PLA) and at least one CPLD macrocell comprising a two-level AND/OR structure;
- a plurality of input/output (I/O) blocks;
- a plurality of segmented interconnect lines;
- a plurality of first programmable multiplexer circuits programmably coupling the CPLD function blocks to the segmented interconnect lines;
- a plurality of second programmable multiplexer circuits programmably coupling the I/O blocks to the segmented interconnect lines;
- and
- a plurality of programmable switch matrices programmably coupling the segmented interconnect lines one to another.
A programmable logic device (PLD), comprising:
- a plurality of complex programmable logic device (CPLD) function blocks disposed to implement a two-dimensional array comprising rows and columns of the CPLD function blocks, each of the CPLD function blocks including a programmable logic array (PLA) and at least one CPLD macrocell comprising a two-level AND/OR structure;
- a plurality of first segmented interconnect lines disposed between adjacent rows of the CPLD function blocks;
- a plurality of second segmented interconnect lines disposed between adjacent columns of the CPLD function blocks;
- and
- a plurality of first programmable multiplexer circuits programmably coupling the CPLD function blocks to the first and second segmented interconnect lines.
A programmable logic device (PLD), comprising:
- a two-dimensional array comprising rows and columns of complex programmable logic device (CPLD) function blocks and input/output (I/O) blocks, each of the CPLD function blocks including a programmable logic array (PLA) and at least one CPLD macrocell comprising a two-level AND/OR structure;
- a programmable interconnect structure disposed between each pair of adjacent rows and each pair of adjacent columns in the array, the programmable interconnect structure comprising a plurality of segmented interconnect lines;
- and
- a plurality of programmable multiplexer circuits programmably coupling the CPLD function blocks and the I/O blocks to the programmable interconnect structure.
Dependencies are inferred from the claim text.