Programmable Logic with Pipelined Memory Operation
AssigneeAltera Corporation
InventorsKok Heng Choe, Edwin Yew Fatt Kok, Kar Keng Chua
Life of this patent
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Abstract
Memory performance of an integrated circuit, such as a programmable logic integrated circuit, is increased by pipelining. In a single clock cycle, more than one operation may be performed on the memory, which improves bandwidth. In an implementation, the memory architecture having one port supports pipelining, so reading from and writing to the memory can be accomplished in a one clock cycle and both Read and Write operation can occupy the full clock cycle at the same time on the same port. The pipelining architecture has relatively minimal circuit changes compared to a standard memory architecture which not supporting simultaneous-clock-cycle reads and writes, without requiring two or more ports.
Claims20
A method of operating a programmable logic integrated circuit comprising:
- in a first portion of a clock cycle, transferring write data through a multiplexer-demultiplexer circuit to a write driver latch;
- in the first portion of the clock cycle, retrieving read data stored in a memory cell of a random access memory;
- in a second portion of the clock cycle, writing the write data from the write driver latch into a memory cell of the random access memory;
- and
- in the second portion of the clock cycle, transferring the read data to an output register.
A method of operating a programmable logic integrated circuit comprising:
- providing a multiplexer-demultiplexer circuit in an enhanced array block of the programmable logic integrated circuit, wherein the multiplexer-demultiplexer circuit is coupled between a memory array, input port, and output port of the enhanced array block;
- in a clock cycle, transferring write data from the input port through the multiplexer-demultiplexer circuit to the memory array;
- and
- in the clock cycle, transferring read data from the memory array through the multiplexer-demultiplexer circuit to the output port wherein at least in a portion of the clock cycle, transferring at least some of the write data and transferring at least some of the read data occur simultaneously.
A programmable logic integrated circuit comprising:
- a plurality of first programmable interconnect conductors arranged in a first direction;
- a plurality of second programmable interconnect conductors arranged in a second direction, different from the first direction;
- a plurality of logic array blocks, programmably coupled to the first and second programmable interconnect conductors;
- and
- a plurality of enhanced array blocks, programmably coupled to the first and second programmable interconnect conductors, each of the enhanced array blocks comprising:
- a write input register;
- a multiplexer-demultiplexer circuit, coupled to the write input register;
- a write latch, coupled to write input register through the multiplexer-demultiplexer circuit;
- a write driver, coupled to the write latch;
- a random access memory, coupled to the write driver;
- a sense amplifier circuit, coupled to the random access memory;
- a first read latch, coupled to the sense amplifier circuit;
- a second read latch, coupled to the first read latch through the multiplexer-demultiplexer circuit;
- and
- a read output register, coupled to the second read latch.
An integrated circuit comprising:
- a programmable interconnect structure to conduct logic signals;
- a clock signal line;
- a plurality of logic array blocks, programmably coupled to the programmable interconnect structure, each logic array block comprising user-configurable logic;
- a memory block, programmably coupled to the clock signal line and the programmable interconnect structure, the memory block comprising a random access memory and a multiplexer-demultiplexer circuit block, wherein at least in a portion of a first cycle of a clock signal on the clock signal line, at least some write data is written to the random access memory and at least some read data is read from the random access memory simultaneously.
Dependencies are inferred from the claim text.