Selectable dynamic reconfiguration of programmable embedded IP
AssigneeAltera Corporation
InventorsVinson Chan, Chong Lee, Rakesh Patel, Ramanand Venkata, Binh Ton
Life of this patent
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Abstract
Improved communication, and an improved communication interface, between the core PLD fabric of a PLD and embedded IP building blocks resident therein is provided. A circuit according to the invention may include at least two different signal paths between the PLD core fabric and embedded IP building blocks. Either one, or both, of these two paths may be used for configuration and/or implementation of the embedded IP building blocks.
Claims20
A programmable logic device comprising:
- a programmable logic device configuration control block;
- a plurality of logic blocks that are programmable based on signals received from the programmable logic device configuration control block;
- a management data input/output configuration control block (MDIO) that converts serial signals received from the logic blocks into parallel signals;
- and
- a plurality of embedded intellectual property building blocks that receive the parallel signals from the MDIO using a first interface.
A method for changing a protocol supported by embedded intellectual property building blocks in a programmable logic device, the method comprising:
- during configuration of the programmable logic device, using a first interface to configure the protocol of the embedded intellectual property building blocks;
- and
- during operation of the programmable logic device, using a second interface to reconfigure the protocol of the embedded intellectual property building blocks.
Dependencies are inferred from the claim text.