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US 7,071,725 B2Granted
Data processing apparatus and logical operation apparatus
AssigneeKabushiki Kaisha Toshiba
InventorKoichi Fujisaki
Life of this patent
Estimating the term…
Abstract
A data processing apparatus comprises a plurality of input signal lines, a plurality of output signal lines and an electronic circuit. The electronic circuit inputs first data from the plurality of input signal lines and outputs second data to the plurality of output signal lines. The first data is one bit data represented by a combination of bits of the plurality of input signal lines. The second data is one bit data represented by a combination of bits of the plurality of output signal lines.
Claims17
An apparatus for processing data, comprising:
- a plurality of input signal lines;
- a plurality of output signal lines;
- an electronic circuit configured to input first data from the plurality of input signal lines and to output second data to the plurality of output signal lines, the first data being one bit data represented by a combination of bits of the plurality of input signal lines, and the second data being one bit data represented by a combination of bits of the plurality of output signal lines,
- wherein the combination of bits of the plurality of signal lines of the one bit data “0” is a first bit status, the combination of bits of the plurality of signal lines of the one bit data “1” is a second bit status, and a hamming weight of the first bit status is equal to a hamming weight of the second bit status;
- and
- an input unit configured to input a control signal representing a distinction between a working phase and an idle phase, the working phase being a period to input and output the first bit status or the second bit status, and the idle phase being a period to input and output a third bit status as the combination of bit status of the plurality of signal lines of invalid data.
3 more elements
A logical operation apparatus, comprising:
- a first data holding circuit configured to input one bit data represented by a combination of bits of two signal lines, to temporarily store the one bit data, and to output the one bit data;
- a second data holding circuit configured to input one bit data represented by a combination of bits of other two signal lines, to temporarily store the one bit data, and to output the one bit data;
- a first logical operation circuit configured to execute a logical operation of a first input data and a second input data, the first input data being a bit status of a first output signal line of the first data holding circuit, the second input data being a bit status of a first output signal line of the second data holding circuit;
- a second logical operation circuit configured to execute a logical operation of a first input data and a second input data, the first input data being a bit status of a second output signal line of the first data holding circuit, the second input data being a bit status of a second output signal line of the second data holding circuit and
- a third data holding circuit configured to input one bit data represented by a combination of bits of an output signal line of the first logical operation circuit and an output signal line of the second logical operation circuit.
2 more elements
A logical operation apparatus, comprising:
- a first data holding circuit configured to input one bit data represented by a combination of bits of two signal lines, to temporarily store the one bit data, and to output the one bit data by a first output signal line and a second output signal line;
- a second data holding circuit configured to input one bit data from a first input signal line and a second input signal line, the one bit data being represented by a reverse combination of bits of the first output signal line and the second output signal line, to temporarily store the one bit data, and to output the one bit data;
- a first inverter configured to input a bit status of the first output signal line, and to output a reverse status of the bit status to the first input signal line of the second data holding circuit;
- and
- a second inverter configured to input a bit status of the second output signal line, and to output a reverse status of the bit status to the second input signal line of the second data holding circuit.
2 more elements
Dependencies are inferred from the claim text.