US 7,071,661 B2 · Method for the dynamically balancing series- and parallel-wired power semiconductor circuits

Abstract

A method for dynamically balancing the loads in a circuit (1, 4) of semiconductor power switches arranged in series or in parallel is disclosed. Individual switching signals (iG1, iG2) for the semiconductor power switches (S1 . . . S4) are generated by determining a system-widely valid synchronous sampling time (tsj) independently for each semiconductor power switch (S1 . . . S4) due to a synchronous event (es) of the whole circuit (1, 4). Control loop offsets between actual values (ai) measured synchronously at the sampling time (tsj) and given desired values (as) of an asynchronous state variable (a(t)) of the semiconductor power switches (S1 . . . S4) are reduced in the same or in following switching cycles. Alternatively, control loop offsets between actual time values (tai) and desired time values (tas) are minimized, wherein the actual time values (tai) are measured upon exceeding a globally provided threshold value (εa) of an asynchronous state variable (a(t)) of the semiconductor power switches (S1 . . . S4). Embodiments relate to: Offsetting the sampling time (tsj) in time by a globally provided time interval (Δt0), providing desired values locally or globally, e.g. by averaging of actual values (ai, tai), additional balancing of the gradients of asynchronous time variables (a(t)). A central sampling command can be dispensed with and the switching synchronicity is improved, switching times are shortened and dynamic switching losses are reduced.

Claims33

Dependent claims

A method for dynamically balancing a circuit of semiconductor power switches, wherein each semiconductor power switch comprises a first power terminal or collector, a second power terminal or emitter and at Least one control terminal or gate, wherein a switching command for initiating a switching process of the circuit is fed to the control terminal and the control terminal can be driven by means of an individual switching signal depending on a control loop offset of a state function of the semiconductor power switch, wherein:

a) the state function is a time-dependent asynchronous state variable, an actual value of which is measured at at least one synchronous sampling time, wherein the synchronous sampling time is determined based on a synchronous event of the circuit for each semiconductor power switch individually, and
b) in the same or in one of the following switching cycles the switching signal is offset in time or its amplitude is varied such that the control loop offset between the actual value and a predefined desired value is reduced.

A method for dynamically balancing a circuit of semiconductor power switches, wherein each semiconductor power switch comprises a first power terminal or collector, a second power terminal or emitter and at least one control terminal or gate, wherein a switching command for initiating a switching process of the circuit is fed to the control terminal and the control terminal can be driven by means of an individual switching signal depending on a control loop offset of a state function of the semiconductor power switch, characterized in that wherein:

a) the state function is chosen equal to a time function in dependence of an asynchronous state variable of the semiconductor power switch, wherein at least one threshold value common to the semiconductor power switches is globally provided for the asynchronous state variable, an individual actual time value being measured for each semiconductor power switch upon exceeding the threshold value,
b) a reference time for the actual time value is locally defined by means of a synchronous event of the circuit, and
c) in the same or one of the following switching cycles the switching signal is offset in time or its amplitude is varied such that the control loop offset between the actual time value and a predefined desired time value is reduced.

Dependencies are inferred from the claim text.

Method for the dynamically balancing series- and parallel-wired power semiconductor circuits

Life of this patent

Method for the dynamically balancing series- and parallel-wired power semiconductor circuits

Life of this patent

Abstract

Claims33