Semiconductor chip capable of implementing wire bonding over active circuits
AssigneeUnited Microelectronics Corp.
InventorsBing-Chang Wu, Kun-Chih Wang, Mei-Ling Chao, Shiao-Shien Chen
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Abstract
A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.
Claims27
A semiconductor chip capable of implementing wire bonding over active circuits, comprising:
- a bonding pad structure;
- at least an interconnection metal layer;
- a metal frame damascened between the bonding pad structure and the interconnection metal layer;
- at least a first via plug beneath the bonding pad structure for electrically linking the bonding pad structure and the interconnection metal layer;
- and
- an active circuit situated beneath the bonding pad structure and on a semiconductor substrate.
An semiconductor chip capable of implementing wire bonding over active circuits comprising:
- a bondable metal pad;
- a top interconnection metal layer situated beneath the bondable metal pad;
- a stress-buffering dielectric situated between the bondable metal pad and the top interconnection metal layer;
- at least a first via plug situated in the stress-buffering dielectric beneath the bondable metal pad for electrically linking the bondable metal pad and the top interconnection metal layer;
- a protection layer covering the stress-buffering dielectric and a portion of the bondable metal pad, and comprising a bonding opening exposing a portion of the top surface of the bondable metal pad to form a bonding window region;
- at least an interconnection metal layer beneath the top interconnection metal layer;
- at least a second via plug situated beneath the bondable metal pad that is covered by the protection layer for electrically linking the top interconnection metal layer and the interconnection metal layer;
- and
- an active circuit situated beneath the bondable metal pad and on a semiconductor substrate.
Dependencies are inferred from the claim text.