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US 7,071,570 B2Granted
Chip scale package and method of fabricating the same
AssigneeSamsung Electro-Mechanics Co., Ltd.
InventorsJoon Ho Yoon, Yong Chil Choi, Suk Su Bae
Life of this patent
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Abstract
A chip scale package has an insulating layer formed on the upper surface of a chip provided with a plurality of terminals on its one surface, a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance so as to be connected to each of a plurality of the terminals, and a plurality of electrode surface layers formed on each of the upper surfaces of a plurality of the conductive layers.
Claims20
A chip scale package, comprising:
- a chip having a plurality of terminals on an upper surface thereof;
- an insulating layer formed on the upper surface of the chip except for the terminals;
- a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance, each of the conductive layers being electrically connected to one of the terminals;
- and
- a plurality of electrode surface layers each being formed on an upper surface of one of the conductive layers;
- wherein the conductive layers and the respective electrode surface layers formed thereon have substantially coplanar side surfaces.
3 more elements
A chip scale package assembly, comprising:
- a chip scale package comprising:
- a chip having a plurality of terminals on an upper surface thereof;
- an insulating layer formed on the upper surface of the chip except for a the terminals;
- a plurality of conductive layers formed on the insulating layer and spaced from each other by a designated distance, each of the conductive layers being electrically connected to one of the terminals;
- and
- a plurality of electrode surface layers each being formed on an upper surface of one of the conductive layers;
- wherein the conductive layers and the respective electrode surface layers formed thereon have substantially coplanar side surfaces;
- and
- a printed circuit board comprising:
- a plurality of connection pads connected to each of the electrode surface layers of the chip scale package;
- and
- circuit patterns connected to each of the connection pads.
9 more elements
A chip scale package, comprising:
- a chip having a plurality of terminals on an upper surface thereof;
- an insulating layer formed on the upper surface of the chip except for the terminals;
- a plurality of conductive layers formed on the insulating layer, each of the conductive layers being electrically connected to one of the terminals;
- a plurality of electrode surface layers each being formed on an upper surface of one of the conductive layers;
- and
- a plurality of unfilled channels, wherein each of the conductive layers and the respective electrode surface layer formed thereon define an island structure which is separated from adjacent island structure or structures by one or more of said channels.
3 more elements
Dependencies are inferred from the claim text.