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US 7,071,554 B2Granted
Stress mitigation layer to reduce under bump stress concentration
AssigneeIntel Corporation
InventorsMakarem A. Hussein, Jun He
Life of this patent
Estimating the term…
Abstract
In some embodiments, the invention provides a stress mitigation layer that reduces stress in a layer of a microelectronic device that is below a conductive connection structure, such as a bump.
Claims14
A device, comprising:
- a dielectric layer;
- a conductive pad on the dielectric layer;
- a stress mitigation layer on the conductive pad, the stress mitigation layer comprising copper and having a thickness in a range of about 2 microns to about 20 microns;
- an insulating layer on the stress mitigation layer;
- and
- a conductive bump having a top bump portion at least partially on the insulating layer and a via portion extending from the top bump portion through the stress mitigation layer to contact the conductive pad.
3 more elements
A device comprising:
- a dielectric layer;
- a conductive pad on the dielectric layer;
- a stress mitigation layer on the conductive pad;
- an insulating layer on the stress mitigation layer;
- and
- a conductive bump having a top bump portion at least partially on the insulating layer and a via portion extending from the top bump portion through the stress mitigation layer to contact the conductive pad;
- wherein the stress mitigation layer has a thickness in a range of about 0.5 microns to about 5 microns.
4 more elements
A microelectronic die, comprising:
- a substrate;
- a interlayer dielectric layer on the substrate;
- a conductive pad on at least a portion of the interlayer dielectric layer;
- a passivation layer on the conductive pad and interlayer dielectric layer;
- a ductile metallic stress mitigation layer comprising copper and having a thickness in a range of about 2 microns to about 20 microns on the passivation layer;
- and
- a conductive bump having a top bump portion above the stress mitigation layer and a via portion extending from the top bump portion through the stress mitigation layer to contact the conductive pad.
4 more elements
A method, comprising:
- forming a dielectric layer on a substrate;
- forming a conductive pad on the dielectric layer;
- forming a passivation layer on the conductive pad;
- forming a patterned ductile metallic stress mitigation layer on the passivation layer, the stress mitigation layer having a thickness in a range of about 1 micron to about 20 microns, the stress mitigation layer patterned to include side walls defining an opening through the stress mitigation layer to the passivation layer;
- forming an insulating layer on the top and side walls of the stress mitigation layer;
- removing a portion of the passivation layer to form an opening through the passivation layer to the conductive pad;
- and
- forming a conductive bump comprising a top bump portion at least partially on the insulating layer and a via portion extending from the top bump portion through the stress mitigation layer to contact the conductive pad.
5 more elements
Dependencies are inferred from the claim text.