# US 7,071,519 B2 · Control of high-k gate dielectric film composition profile for property optimization

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- Number: US 7,071,519 B2
- Document ID: US7071519B2
- Status: Granted
- Kind: B2
- Application number: 10/338,310
- Filed: 2003-01-08
- Published: 2004-07-08
- Granted: 2006-07-04
- Earliest claimed: 2003-01-08
- Assignees: Texas Instruments Incorporated
- Inventors: Luigi Colombo; Mark Visokay; James Joseph Chambers; Antonio Luis Pacheco Rotondaro
- Web page: https://patentgrep.com/patent/US7071519B2

## CPC

- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 1/684: {the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.

## Claims

### Claim 1

A method of fabricating a semiconductor device comprising:
forming a plurality of dielectric sub-layers using chemical vapor deposition, said plurality of dielectic sub-layers having respective relative composition ratios on a substrate, wherein the plurality of dielectric sub-layers define a dielectric layer having a particular relative composition profile and wherein the particular relative compostion profile is substantially constant;
forming a gate electrode on the dielectric layer;
patterning the gate electrode and the dielectric layer therein defining a gate stack; and
forming a source region and a drain region within the substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the substrate is comprised at least partly of silicon and wherein the dielectric layer is at least partly comprised of silicon, wherein forming the plurality of dielectric sub-layers further comprises forming a lower interface dielectric sub-layer on the substrate that has a relatively high ratio of silicon and that facilitates bonding to the substrate.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the plurality of dielectric sub-layers further comprises forming an upper interface dielectric sub-layer that has a relatively high ratio of silicon, wherein the gate is comprised of polysilicon or silicon-germanium and wherein forming the gate further comprises forming a bond with the upper interface dielectric sub-layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the plurality of dielectric sub-layers further comprises forming an upper interface dielectric sub-layer that has a relatively high ratio of a metal material, wherein the gate is comprised of the metal material and wherein forming the gate further comprises forming a bond with the upper interface dielectric sub-layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the particular relative composition profile varies by less than about one percent.