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US 7,071,509 B2Granted
Method of improving the top plate electrode stress inducting voids for 1T-RAM process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorKuo-Chi Tu
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Abstract
A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlying the stress-balancing layer. The stack is patterned to form the capacitors. Gate transistors are formed overlying the capacitors wherein the stress-balancing layer prevents formation of stress-induced voids during the thermal processes involved in forming the gate transistors.
Claims8
An integrated circuit device comprising:
- a bottom electrode of a capacitor formed lining trenches within shallow trench isolation regions within a substrate;
- a capacitor dielectric layer overlying said bottom electrode;
- a top electrode layer overlying the capacitor dielectric layer within and overlying said shallow isolation regions;
- a stress-balancing dielectric layer overlying said top electrode of said capacitor;
- an anti-reflective coating (ARC) layer overlying said stress-balancing layer;
- a gate oxide layer overlying said substrate;
- and
- transistor gates overlying said gate oxide layer and said ARC layer over said capacitor.
5 more elements
Dependencies are inferred from the claim text.